AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 58

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Table 2-19 • Flash Memory Block Pin Names
2- 42
Interface Name
ADDR[17:0]
AUXBLOCK
BUSY
CLK
DATAWIDTH[1:0]
DISCARDPAGE
ERASEPAGE
LOCKREQUEST
OVERWRITEPAGE
OVERWRITEPROTECT
PAGESTATUS
PAGELOSSPROTECT
PIPE
PROGRAM
RD[31:0]
READNEXT
REN
RESET
SPAREPAGE
Flash Memory Block Pin Names
Width Direction
18
32
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
Out
Out
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
Byte offset into the FB. Byte-based address.
When asserted, the page addressed is used to access the auxiliary
block within that page.
When asserted, indicates that the FB is performing an operation.
User interface clock. All operations and status are synchronous to the
rising edge of this clock.
Data width
00 = 1 byte in RD/WD[7:0]
01 = 2 bytes in RD/WD[15:0]
1x = 4 bytes in RD/WD[31:0]
When asserted, the contents of the Page Buffer are discarded so that
a new page write can be started.
When asserted, the address page is to be programmed with all zeros.
ERASEPAGE must transition synchronously with the rising edge of
CLK.
When asserted, indicates to the JTAG controller that the FPGA
interface is accessing the FB.
When asserted, the page addressed is overwritten with the contents of
the Page Buffer if the page is writable.
When asserted, all program operations will set the overwrite protect bit
of the page being programmed.
When asserted with REN, initiates a read page status operation.
When asserted, a modified Page Buffer must be programmed or
discarded before accessing a new page.
Adds a pipeline stage to the output for operation above 50 MHz.
When asserted, writes the contents of the Page Buffer into the FB
page addressed.
Read data; data will be valid from the first non-busy cycle (BUSY = 0)
after REN has been asserted.
When asserted with REN, initiates a read-next operation.
When asserted, initiates a read operation.
When asserted, resets the state of the FB (active low).
When asserted, the sector addressed is used to access the spare
page within that sector.
R e visio n 1
Description