AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 39

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Conditioning Circuits
In Fusion devices, the CCCs are used to implement frequency division, frequency multiplication, phase
shifting, and delay operations.
The CCCs are available in six chip locations—each of the four chip corners and the middle of the east
and west chip sides.
Each CCC can implement up to three independent global buffers (with or without programmable delay),
or a PLL function (programmable frequency division/multiplication, phase shift, and delays) with up to three
global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up
to a maximum of three global outputs for a given CCC.
A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC-
GLC) of a given CCC.
A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and, optionally, the
GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC
regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used
(Figure
Each global buffer, as well as the PLL reference clock, can be driven from one of the following:
The CCC block is fully configurable, either via flash configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous interface is dynamically accessible from inside
the Fusion device to permit changes of parameters (such as divide ratios) during device operation. To
increase the versatility and flexibility of the clock conditioning system, the CCC configuration is
determined either by the user during the design process, with configuration data being stored in flash
memory as part of the device programming procedure, or by writing data into a dedicated shift register
during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC
without the need for core programming. The shift register is accessed through a simple serial interface.
Refer to the "UJTAG Applications in Actel’s Low-Power Flash Devices" chapter of the
Fabric User’s Guide
•
•
•
3 dedicated single-ended I/Os using a hardwired connection
2 dedicated differential I/Os using a hardwired connection
The FPGA core
2-19). Refer to the
and the
"PLL Macro" section on page 2-29
"CCC and PLL Characteristics" section on page 2-30
R e v i s i o n 1
for more information.
Actel Fusion Family of Mixed Signal FPGAs
for more information.
Fusion FPGA
2- 23