AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 47

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

No-Glitch MUX (NGMUX)
Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence
between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses.
The NGMUX is used to switch the source of a global between three different clock sources. Allowable
inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or
GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring
the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global
network (GL). See
Figure 2-24 • NGMUX
Table 2-13 • NGMUX Configuration and Selection Table
GLMUXCFG[1:0]
00
01
W I/O Ring
CCC/PLL
Table
Clock I/Os
From FPGA Core
Crystal Oscillator
2-13.
RC Oscillator
GLMUXSEL[1:0]
X
X
X
X
PLL/
CCC
GLINT
R e v i s i o n 1
GLA
GLC
PWR UP
GLMUXSEL[1:0]
NGMUX
GLMUXCFG[1:0]
0
1
0
1
Actel Fusion Family of Mixed Signal FPGAs
Selected Input
Signal
GLINT
GLC
GLA
GLA
To Clock Rib Driver
GL
2-to-1 GLMUX
2-to-1 GLMUX
MUX Type
Figure
2-24.
2- 31