LFE2M20SE-5FN484C Lattice, LFE2M20SE-5FN484C Datasheet - Page 129

• Manufacturer Part Number: LFE2M20SE-5FN484C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN484C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 304
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP
Number
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
1
2
3
4
5
6
7
8
9
LLM0_PLLCAP
Function
VCCAUX
VCCAUX
VCCIO7
VCCIO7
VCCIO6
VCCIO6
Pin/Pad
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL20A
PL21A
PL20B
PL21B
PL23A
PL24A
PL24B
PL26A
PL26B
PL28A
PL2A
PL2B
PL4A
PL4B
PL6A
PL6B
PL8A
PL8B
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
Bank
LFE2-12E/SE
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
LLM0_GDLLC_IN_A**
LLM0_GPLLC_IN_A**
LLM0_GDLLT_IN_A**
LLM0_GPLLT_IN_A**
LLM0_GPLLC_FB_A
LLM0_GPLLT_FB_A
PCLKT7_0/LDQ10
PCLKC7_0/LDQ10
PCLKC6_0
PCLKT6_0
VREF2_6
VREF1_6
Function
VREF2_7
VREF1_7
LDQS28
LDQ10
LDQ10
LDQ10
LDQ10
LDQ10
LDQ28
LDQ28
LDQ28
LDQ28
LDQ10
Dual
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
T
T
T
4-26
LLM0_PLLCAP
Function
VCCAUX
VCCAUX
VCCIO7
VCCIO7
VCCIO6
VCCIO6
Pin/Pad
PL12A
PL12B
PL14A
PL14B
PL18A
PL18B
PL19A
PL19B
PL21A
PL21B
PL22A
PL22B
PL27A
PL27B
PL30A
PL31A
PL30B
PL31B
PL33A
PL38A
PL38B
PL40A
PL40B
PL42A
PL2A
PL2B
PL6A
PL6B
GND
VCC
GND
GND
VCC
GND
VCC
GND
VCC
GND
LatticeECP2/M Family Data Sheet
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
LLM0_GDLLC_IN_A**/LDQ25
LLM0_GPLLC_IN_A**/LDQ34
LLM0_GDLLT_IN_A**/LDQ25
LLM0_GPLLT_IN_A**/LDQ34
LLM0_GPLLC_FB_A/LDQ34
LLM0_GPLLT_FB_A/LDQ34
LFE2-20E/SE
PCLKT7_0/LDQ16
PCLKC7_0/LDQ16
PCLKC6_0/LDQ25
PCLKT6_0/LDQ25
VREF2_6/LDQ25
VREF1_6/LDQ25
Function
VREF2_7
VREF1_7
LDQS42
LDQ16
LDQ16
LDQ16
LDQ16
LDQ16
LDQ16
LDQ34
LDQ42
LDQ42
LDQ42
LDQ42
LDQ8
LDQ8
Dual
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
T
T
T