A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 81

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-95 • A3PE600 Global Resource
Table 2-96 • A3PE1500 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Timing Characteristics
Description
Description
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.425 V
R e v i s i o n 9
Table 2-6 on page 2-5
Table 2-6 on page 2-5
Min.
Min.
0.83
0.81
1.07
1.06
1
1
–2
–2
Max.
Max.
1.29
1.32
0.26
1.04
1.06
0.25
2
2
Min.
Min.
1.22
1.21
0.94
0.93
1
1
–1
–1
for derating values.
for derating values.
ProASIC3E Flash Family FPGAs
Max.
Max.
1.47
1.50
0.29
1.18
1.21
0.28
2
2
Min.
Min.
1.43
1.42
1.11
1.09
Std.
1
Std.
1
Max.
Max.
1.72
1.76
0.34
1.39
1.42
0.33
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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