MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 35

• Manufacturer Part Number: MSC8144VT800A
• Description: IC DSP QUAD 800MHZ 783FCBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144VT800A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 800MHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.6
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144 device:
Note:
Figure 6
2.6.2
The following sections include a description of clock signal characteristics.
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Freescale Semiconductor
CLKIN frequency
PCI_CLK_IN frequency
CLKIN duty cycle
PCI_CLK_IN duty cycle
•
•
•
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the V
supply. See
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
V
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
(see
CLKIN and PCI_CLK_IN should either be stable low during the power-up of V
power-up or should swing within V
during power-up.
shows a sequence in which
DDM3IO
Figure 6. Start-Up Sequence with V
AC Timings
Figure
Start-Up Timing
Clock and Timing Signals
PORESET/TRST asserted
(2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.
6). 32 cycles should be accounted only after V
Table 19
V
DD
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Characteristic
3.3 V
1.0 V
for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
applied
V
DDIO
is raised after
DDIO
Table 16. Clock Frequencies
V
DDIO
range during V
CLKIN starts toggling
DD
applied
Raised Before
V
DD
and
DDIO
CLKIN
DDIO
V
V
1
DD
DDIO
power-up., so their amplitude grows as V
reaches its nominal value.
= Nominal
V
begins to toggle with the raise of
F
D
Table 16
Symbol
= Nominal
DDIO
PCI_CLK_IN
PCI_CLK_IN
F
D
CLKIN
CLKIN
PORESET
with CLKIN Started with
shows the maximum frequency values for
DDIO
V
Min
33
33
40
40
V
DD
Time
supply and start their swings after
DDIO
Nominal
Nominal
Electrical Characteristics
Max
133
133
60
60
V
DDIO
V
DDIO
DDIO
DDIO
supply.
Unit
grows
MHz
MHz
(3.3 V)
%
%
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