MSC8144SVT1000A Freescale Semiconductor, MSC8144SVT1000A Datasheet - Page 61

• Manufacturer Part Number: MSC8144SVT1000A
• Description: IC DSP QUAD 1GHZ 783FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144SVT1000A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 1.0GHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.6.12
Table 48
Figure 34
Figure 35
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 35
Figure 36
Freescale Semiconductor
SPI outputs valid—Master mode (internal clock) delay
SPI outputs hold—Master mode (internal clock) delay
SPI outputs valid—Slave mode (external clock) delay
SPI outputs hold—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock input) setup time
SPI inputs—Master mode (internal clock) input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
lists the SPI input and output AC timing specifications.
1.
2.
provides the AC test load for the SPI.
and
shows the SPI timings in slave mode (external clock).
shows the SPI timings in master mode (internal clock).
Note: The clock edge is selectable on SPI.
Output Signals:
SPICLK (Input)
Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
The symbols for timing specifications follow the pattern of t
t
the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
SPI Timing
Figure 36
(first two letters of functional block)(reference)(state)(signal)(state)
Input Signals:
(See Note)
(See Note)
SPIMOSI
SPIMISO
represent the AC timings from
Output
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Characteristic
Figure 35. SPI AC Timing in Slave Mode (External Clock)
t
NEIVKH
Table 48. SPI AC Timing Specifications
t
NIKHOX
Figure 34. SPI AC Test Load
Z
0
= 50 Ω
Table
for outputs. For example, t
48. Note that although the specifications generally reference the
t
NEIXKH
t
NIKHOV
(first two letters of functional block)(signal)(state) (reference)(state)
Symbol
t
t
t
t
t
t
NEKHOV
NEKHOX
t
t
NIKHOV
NIKHOX
NEIVKH
NEIXKH
NIIVKH
NIIXKH
R
L
= 50 Ω
2
NIKHOX
1
OV
symbolizes the internal timing (NI) for
Min
0.5
2
4
0
4
2
DD
/2
Max
6
8
for inputs and
Unit
ns
ns
ns
ns
ns
ns
ns
ns
61