IC ARM CORTEX 1MB 144LQFP

STM32F101ZGT6

Manufacturer Part NumberSTM32F101ZGT6
DescriptionIC ARM CORTEX 1MB 144LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101ZGT6 datasheet
 


Specifications of STM32F101ZGT6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o112
Program Memory Size1MB (1M x 8)Program Memory TypeFLASH
Ram Size80K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12b; D/A 2x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case144-LFQFP
Processor SeriesSTM32F101xGCoreARM Cortex M3
Data Bus Width32 bitData Ram Size80 KB
Interface TypeI2C, SPI, UARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os112Number Of Timers15
Operating Supply Voltage2 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTOperating Temperature Range- 40 C to + 105 C
Processor To Be EvaluatedSTM32F101ZGSupply Current (max)28 mA
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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XL-density access line, ARM-based 32-bit MCU with 768 KB
to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU with MPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance
– Single-cycle multiplication and hardware
division
Memories
– 768 Kbytes to 1 Mbyte of Flash memory
(dual bank with read-while-write capability)
– 80 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND
memories
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
capability
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
1 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
2 × 12-bit D/A converters
DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, DAC,
2
SPIs, I
Cs and USARTs
Up to 112 fast I/O ports
November 2010
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
P144
LQF
20 × 2
0 mm
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
Up to 15 timers
– Up to ten 16-bit timers, with up to 4
IC/OC/PWM or pulse counters
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
Up to 10 communication interfaces
2
– Up to 2 x I
C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s)
CRC calculation unit, 96-bit unique ID
®
ECOPACK
packages
Table 1.
Device summary
Reference
STM32F101RF STM32F101VF
STM32F101xF
STM32F101ZF
STM32F101RG STM32F101VG
STM32F101xG
STM32F101ZG
Doc ID 17143 Rev 2
STM32F101xF
STM32F101xG
Preliminary data
LQFP100
LQFP64
×
14
14 mm
×
10
10 mm
Part number
1/108
www.st.com
1

STM32F101ZGT6 Summary of contents

  • Page 1

    XL-density access line, ARM-based 32-bit MCU with 768 Flash, 15 timers, 1 ADC and 10 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU with MPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance ...

  • Page 2

    Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM32F101xF, STM32F101xG 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM32F101xF, STM32F101xG Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM32F101xF, STM32F101xG List of figures Figure 1. STM32F101xF and STM32F101xG access line block diagram . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Clock tree ...

  • Page 8

    List of figures Figure 41 tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 9

    ... This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xF and STM32F101xG XL-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Full compatibility throughout the The XL-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual ...

  • Page 10

    Description 2 Description The STM32F101xF and STM32F101xG access line family incorporates the high- performance ARM speed embedded memories (Flash memory Mbyte and SRAM of 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to ...

  • Page 11

    STM32F101xF, STM32F101xG 2.1 Device overview The STM32F101xx XL-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an ...

  • Page 12

    Description Figure 1. STM32F101xF and STM32F101xG access line block diagram TRACECLK TRACED[0:3] TPIU as AS SW/JTAG NJTRST JTDI JTCK/SWCLK Cortex-M3 CPU JTMS/SWDIO JTDO as AF A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT 112AF PA[15:0] PB[15:0] PC[15:0] ...

  • Page 13

    STM32F101xF, STM32F101xG Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz have an ADC conversion time of 1 µs, APB2 ...

  • Page 14

    Description 2.2 Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are ...

  • Page 15

    STM32F101xF, STM32F101xG 2.3 Overview ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the ...

  • Page 16

    Description 2.3.5 Embedded SRAM 80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has four ...

  • Page 17

    STM32F101xF, STM32F101xG 2.3.10 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it ...

  • Page 18

    Description 2.3.14 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is ...

  • Page 19

    STM32F101xF, STM32F101xG 2.3.17 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on V supply when present or through the V DD registers used to store 84 bytes ...

  • Page 20

    Description one-pulse mode output. This gives input captures / output compares / PWMs on the largest packages. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. ...

  • Page 21

    STM32F101xF, STM32F101xG 2.3.19 I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification ...

  • Page 22

    Description The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.24 DAC (digital-to-analog converter) The two 12-bit buffered ...

  • Page 23

    STM32F101xF, STM32F101xG 3 Pinouts and pin descriptions Figure 3. STM32F101xF and STM32F101xG access line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 ...

  • Page 24

    Pinouts and pin descriptions Figure 4. STM32F101xF and STM32F101xG LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP 24/108 PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

  • Page 25

    STM32F101xF, STM32F101xG Figure 5. STM32F101xF and STM32F101xG LQFP64 pinout V BAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 V SSA V DDA PA0-WKUP PA1 PA2 Table 5. STM32F101xF and STM32F101xG pin definitions Pins Pin name 1 - ...

  • Page 26

    Pinouts and pin descriptions Table 5. STM32F101xF and STM32F101xG pin definitions (continued) Pins Pin name PF6 PF7 PF8 PF9 PF10 OSC_IN 24 ...

  • Page 27

    STM32F101xF, STM32F101xG Table 5. STM32F101xF and STM32F101xG pin definitions (continued) Pins Pin name PA7 PC4 PC5 PB0 PB1 PB2 ...

  • Page 28

    Pinouts and pin descriptions Table 5. STM32F101xF and STM32F101xG pin definitions (continued) Pins Pin name PB13 PB14 PB15 PD8 PD9 PD10 80 ...

  • Page 29

    STM32F101xF, STM32F101xG Table 5. STM32F101xF and STM32F101xG pin definitions (continued) Pins Pin name 104 45 71 PA12 105 46 72 PA13 106 - 73 107 SS_2 108 DD_2 109 49 76 PA14 110 50 ...

  • Page 30

    ... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...

  • Page 31

    STM32F101xF, STM32F101xG Table 6. FSMC pin definition Pins CF PE2 PE3 PE4 PE5 PE6 PF0 A0 PF1 A1 PF2 A2 PF3 A3 PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF11 NIOS16 PF12 A6 ...

  • Page 32

    Pinouts and pin descriptions Table 6. FSMC pin definition (continued) Pins CF PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT ...

  • Page 33

    STM32F101xF, STM32F101xG 4 Memory mapping The memory map is shown in Figure 6. Memory map 0xFFFF FFFF 512-Mbyte block 7 Cortex-M3's internal 0xE000 0000 peripherals 0xDFFF FFFF 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC ...

  • Page 34

    Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 35

    STM32F101xF, STM32F101xG 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin loading conditions C=50pF 5.1.6 Power supply scheme Figure 9. Power supply scheme Caution: In Figure 9, the 4.7 ...

  • Page 36

    Electrical characteristics 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional ...

  • Page 37

    STM32F101xF, STM32F101xG Table 8. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

  • Page 38

    Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock frequency PCLK2 V Standard operating voltage DD Analog operating ...

  • Page 39

    STM32F101xF, STM32F101xG . Table 12. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power on/power down V POR/PDR reset threshold (2) V PDR hysteresis PDRhyst (2) t Reset ...

  • Page 40

    Electrical characteristics 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 13. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when reading (1) T S_vrefint the internal reference voltage Internal reference voltage ...

  • Page 41

    STM32F101xF, STM32F101xG Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 MHz ...

  • Page 42

    Electrical characteristics Figure 11. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled Figure 12. Typical current consumption in Run ...

  • Page 43

    STM32F101xF, STM32F101xG Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 MHz ...

  • Page 44

    Electrical characteristics Figure 13. Typical current consumption on V different V 2.5 2 1.5 1 0.5 0 Figure 14. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V 300 250 200 150 100 ...

  • Page 45

    STM32F101xF, STM32F101xG Figure 15. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V 300 250 200 150 100 50 0 Figure 16. Typical current consumption in Standby mode versus temperature at different V ...

  • Page 46

    Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V ● All peripherals are disabled except explicitly mentioned ● The ...

  • Page 47

    STM32F101xF, STM32F101xG Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of 0.8 ...

  • Page 48

    Electrical characteristics Table 20. Peripheral current consumption Peripheral APB1 48/108 Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 SPI2 SPI3 USART2 USART3 USART4 USART5 I2C1 I2C2 CAN (2) DAC Doc ID 17143 Rev 2 ...

  • Page 49

    STM32F101xF, STM32F101xG Table 20. Peripheral current consumption (continued) Peripheral APB2 MHz, f HCLK 2. Specific conditions for DAC: EN1, EN2 bits in the DAC_CR register are set to 1 and the converted value set to 0x800. ...

  • Page 50

    Electrical characteristics Table 21. High-speed external user clock characteristics Symbol User external clock source f HSE_ext frequency OSC_IN input pin high level V HSEH voltage OSC_IN input pin low level V HSEL voltage t w(HSE) OSC_IN high or low time ...

  • Page 51

    STM32F101xF, STM32F101xG Figure 17. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 18. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...

  • Page 52

    Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained ...

  • Page 53

    STM32F101xF, STM32F101xG Figure 19. Typical application with an 8 MHz crystal Resonator with integrated capacitors value depends on the crystal characteristics. EXT Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can ...

  • Page 54

    Electrical characteristics Note: For C and recommended to use high-quality ceramic capacitors in the range selected to match the requirements of the crystal or resonator. C usually the same ...

  • Page 55

    STM32F101xF, STM32F101xG 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC ...

  • Page 56

    Electrical characteristics 5.3.8 PLL characteristics The parameters given in temperature and V Table 28. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT t PLL lock time LOCK Jitter Cycle-to-cycle ...

  • Page 57

    STM32F101xF, STM32F101xG Table 30. Flash memory endurance and data retention Symbol N Endurance END t Data retention RET 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms and ...

  • Page 58

    Electrical characteristics Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to ...

  • Page 59

    STM32F101xF, STM32F101xG Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Preliminary values. Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE ...

  • Page 60

    Electrical characteristics Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Preliminary values. Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms FSMC_NE FSMC_NOE ...

  • Page 61

    STM32F101xF, STM32F101xG Table 33. Asynchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_BL hold time after FSMC_NOE high h(BL_NOE) t FSMC_NEx low to FSMC_BL valid v(BL_NE) t Data to FSMC_NEx high setup time su(Data_NE) t Data to FSMC_NOE high setup time ...

  • Page 62

    Electrical characteristics Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 34. Asynchronous multiplexed NOR/PSRAM write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

  • Page 63

    STM32F101xF, STM32F101xG Synchronous waveforms and timings Figure 25 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

  • Page 64

    Electrical characteristics Table 35. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK high to FSMC_NEx high (x = 0...2) d(CLKH-NExH) t FSMC_CLK low to FSMC_NADV low ...

  • Page 65

    STM32F101xF, STM32F101xG Figure 26. Synchronous multiplexed PSRAM write timings t w(CLK) FSMC_CLK FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] FSMC_NWE t d(CLKL-ADV) FSMC_AD[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL t w(CLK) Data latency = 1 t d(CLKL-NExL) t d(CLKL-NADVH) t ...

  • Page 66

    Electrical characteristics Table 36. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH) ...

  • Page 67

    STM32F101xF, STM32F101xG Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) Table 37. Synchronous non-multiplexed NOR/PSRAM ...

  • Page 68

    Electrical characteristics Figure 28. Synchronous non-multiplexed PSRAM write timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 38. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t ...

  • Page 69

    STM32F101xF, STM32F101xG PC Card/CompactFlash controller waveforms and timings Figure 29 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime ...

  • Page 70

    Electrical characteristics Figure 30. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 70/108 High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...

  • Page 71

    STM32F101xF, STM32F101xG Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High t ...

  • Page 72

    Electrical characteristics Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 33. PC Card/CompactFlash controller ...

  • Page 73

    STM32F101xF, STM32F101xG Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = ...

  • Page 74

    Electrical characteristics Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_D[15:0] valid before FSMC_NWE high d(D-NWE) t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) ...

  • Page 75

    STM32F101xF, STM32F101xG Figure 35. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 36. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 37. NAND controller ...

  • Page 76

    Electrical characteristics Figure 38. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 40. Switching characteristics for NAND Flash read and write cycles Symbol (2) t FSMC_D[15:0] valid before FSMC_NWE high d(D-NWE) ...

  • Page 77

    STM32F101xF, STM32F101xG 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by ...

  • Page 78

    Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test ...

  • Page 79

    STM32F101xF, STM32F101xG 5.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. However, ...

  • Page 80

    Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 46. I/O static characteristics Symbol Parameter Standard IO input low level voltage V IL (1) IO ...

  • Page 81

    STM32F101xF, STM32F101xG Figure 39. Standard I/O input characteristics - CMOS port Figure 40. Standard I/O input characteristics - TTL port Doc ID 17143 Rev 2 Electrical characteristics 81/108 ...

  • Page 82

    Electrical characteristics Figure 41 tolerant I/O input characteristics - CMOS port Figure 42 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, ...

  • Page 83

    STM32F101xF, STM32F101xG Output voltage levels Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Output Low level voltage for an I/O ...

  • Page 84

    Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 48, respectively. Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. Table 48. I/O AC characteristics MODEx ...

  • Page 85

    STM32F101xF, STM32F101xG Figure 43. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved 2/3)T and if the duty cycle is (45-55%) 5.3.15 NRST pin characteristics The NRST pin input ...

  • Page 86

    Electrical characteristics 5.3.16 TIM timer characteristics The parameters given in Refer to Section 5.3.14: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx Symbol t Timer resolution time res(TIM) Timer external clock f ...

  • Page 87

    STM32F101xF, STM32F101xG 2 Table 51 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...

  • Page 88

    Electrical characteristics 2 Figure 45 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 52. SCL frequency ( External pull-up resistance For speeds around 200 ...

  • Page 89

    STM32F101xF, STM32F101xG SPI interface characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table Refer to Section 5.3.14: I/O port characteristics function characteristics (NSS, SCK, MOSI, MISO). Table 53. STM32F10xxx SPI characteristics Symbol Parameter ...

  • Page 90

    Electrical characteristics Table 54. SPI characteristics Symbol f SCK SPI clock frequency 1/t c(SCK) t SPI clock rise and fall r(SCK) t time f(SCK) SPI slave input clock duty DuCy(SCK) cycle (2) t NSS setup time su(NSS) (2) t NSS ...

  • Page 91

    STM32F101xF, STM32F101xG Figure 46. SPI timing diagram - slave mode and CPHA=0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure 47. SPI ...

  • Page 92

    Electrical characteristics Figure 48. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 5.3.18 ...

  • Page 93

    STM32F101xF, STM32F101xG Table 55. ADC characteristics Symbol V Power supply DDA V Positive reference voltage REF+ Current on the V I VREF pin f ADC clock frequency ADC (2) Sampling rate f S (2) f External trigger frequency TRIG V ...

  • Page 94

    Electrical characteristics The formula above allowed for an error below 1/4 of LSB. Here (from 12-bit resolution). Table 56. R AIN T (cycles) s 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Guaranteed by design, not ...

  • Page 95

    STM32F101xF, STM32F101xG Table 58. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be ...

  • Page 96

    Electrical characteristics Figure 50. Typical connection diagram using the ADC V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7 pF). ...

  • Page 97

    STM32F101xF, STM32F101xG Figure 52. Power supply and reference decoupling ( and V REF+ REF- 5.3.19 DAC electrical specifications Table 59. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) ...

  • Page 98

    Electrical characteristics Table 59. DAC characteristics (continued) Symbol Parameter DAC DC current consumption I in quiescent mode (Standby DDVREF+ mode) DAC DC current consumption I in quiescent mode (Standby DDA mode) Differential non linearity (3) DNL Difference between two consecutive ...

  • Page 99

    STM32F101xF, STM32F101xG Figure 53. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer ...

  • Page 100

    Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

  • Page 101

    STM32F101xF, STM32F101xG Figure 54. LQFP144 mm, 144-pin thin quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...

  • Page 102

    Package characteristics Figure 56. LQFP100 – mm, 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...

  • Page 103

    STM32F101xF, STM32F101xG Figure 58. LQFP64 – mm, 64 pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions are ...

  • Page 104

    Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: ● T max is the maximum ambient temperature in °C, A  ...

  • Page 105

    STM32F101xF, STM32F101xG 6.2.2 Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature ...

  • Page 106

    Part numbering 7 Part numbering Table 65. STM32F101xF and STM32F101xG ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count pins V = ...

  • Page 107

    STM32F101xF, STM32F101xG 8 Revision history Table 66. Document revision history Date Revision 27-Oct-2009 15-Nov-2010 1 Initial release. LQFP64 package mechanical data updated: see mm, 64 pin low-profile quad flat package outline LQFP64 – mm, ...

  • Page 108

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...