D2-45157-QR Intersil, D2-45157-QR Datasheet - Page 20

• Manufacturer Part Number: D2-45157-QR
• Description: IC DGTL AMP PWM CTRLR 68QFN
• Manufacturer: Intersil
• Series: D2Audio™r
• Type: Class Dr

Specifications of D2-45157-QR

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 30W x 2 @ 8 Ohm
• Voltage - Supply: 9 V ~ 26 V
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Control Interface Address Spaces
Registers are accessed through the I
using the I
the device or product under control through I
communication as the D2-45057, D2-45157.
Registers and memory spaces are defined within the
D2-45057, D2-45157 for specific internal operation and
control. The highest-order byte of the register address
(bits 23:16) determines the internal address space used
for control read or write access, and the remaining 16
bits (bits 15:0) describe the actual address within that
space.
Programmable settings for the audio processing blocks
are internally mapped to the address space defined with
the highest order bits all zero. (For example, 0x00nnnn,
where nnnn is the address location within this address
space.)
Storing Parameters to EEPROM
The D2-45057, D2-45157 device has the ability to store
parameters data to an EEPROM. If an EEPROM is installed
in the application, the programmable parameter data can
be saved in this EEPROM. This stored data can then be
recalled upon reset or power-up.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an alternate serial
input port that provides an interface for loading
parameter data from an optional EEPROM or Flash device
during boot-up operation.
The four SPI interface pins are all shared functions:
• Following a reset condition and while the device is
Read Sequence
Write Sequence
initiating the boot-up process, these four SPI pins
START
START
2
C channel address of 0xB2. This establishes
DEVICE-ADDR
DEVICE-ADDR
ACK
REPEAT
START
20
R/W
R/W
DEVICE-ADDR
ACK
ACK
REGISTER [7:0]
FIGURE 14. I
FIGURE 15. I
2
REGISTER [23:16]
REGISTER [23:16]
C control interface,
R/W
D2-45057, D2-45157
ACK
ACK
2
C
2
C WRITE SEQUENCE OPERATION
2
C READ SEQUENCE OPERATION
ACK
ACK
DATA [23:16]
DATA [23:16]
Step 1
REGISTER [15:8]
REGISTER [15:8]
• As soon as the boot-up process is completed and the
Refer to multiple-purpose pins descriptions in Table 5 for
more description of these pin functions.
Reset and Device Initialization
The D2-45057, D2-45157 devices must be reset to
initialize and begin proper operation. A system reset is
initiated by applying a low level to the nRESET input
pin. External hardware circuitry or a controller within
the amplifier system design must provide this reset
signal and connect to the nRESET input to initiate the
reset process. Device initialization then begins after the
nRESET pin is released from its low-active state.
The chip contains power rail sensors and brownout
detectors on the 3.3V RVDD and PWMVDD power
supplies, and the 1.8V CVDD power supply. A loss or
droop of power from these supplies will trigger their
brownout detectors which will assert the nRSTOUT
output pin, driving it low. The nRSTOUT pin should
connect to the nRESET input through hardware on the
amplifier design, to ensure a proper reset occurs if the
power supply voltages drop below their design
specifications.
At the de-assertion of nRESET, the chip will read the
status of the boot mode selection pins (IRQA and IRQB)
and begin the boot process, determined by the boot
(TEMPREF/SCK, TEMP1/MOSI, VOL1/MISO,
VOL0/nSS) function as an SPI input port for external
boot loading operation.
device begins executing its firmware program, these
pins are no longer used for SPI functions, and are
reassigned by the firmware for use as
dedicated-function I/O for amplifier operation.
MASTER
ACK
Step 2
ACK
ACK
ACK
DATA [15:8]
DATA [15:8]
REGISTER [7:0]
REGISTER [7:0]
MASTER
ACK
ACK
ACK
DATA [7:0]
DATA [7:0]
REPEAT
START
July 29, 2010
NACK
ACK
FN6785.0
STOP
STOP