PC28F128P30B85A NUMONYX, PC28F128P30B85A Datasheet - Page 63

• Manufacturer Part Number: PC28F128P30B85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P30B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 873877; 873877; PC28F128P30B85; PC28F128P30B85 873877

P30
15.4
Table 33: AC Write Specifications
August 2008
Order Number: 306666-12
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W16
Write to Asynchronous Read Specifications
W18
Write to Synchronous Read Specifications
W19
W20
Write Specifications with Clock Active
W21
W22
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Num
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
(whichever occurs first). Hence, t
Write pulse width high (t
(whichever occurs last). Hence, t
t
V
This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and
W20 for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
WHVH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
PHWL
ELWL
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
VPWH
QVVL
QVBL
BHWH
WHGL
WHQV
WHAV
WHCH/L
WHVH
VHWL
CHWL
Symbol
and WP# should be at a valid level until erase or program success is determined.
or t
AC Write Specifications
WHCH/L
RST# high recovery to WE# low
CE# setup to WE# low
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
V
V
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
WE# high to read valid
WE# high to Address valid
WE# high to Clock valid
WE# high to ADV# high
ADV# high to WE# low
Clock high to WE# low
must be met when transitioning from a write cycle to a synchronous burst read.
PP
PP
setup to WE# high
hold from Status read
WLWH
WHWL
or t
or t
ELEH
WHWL
WLWH
EHEL
Parameter
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
= t
= t
EHEL
ELEH
= t
= t
WHEL
WLEH
= t
= t
EHWL
ELWH
).
.
t
AVQV
Min
150
200
200
50
50
50
20
19
19
0
0
0
0
0
0
0
0
-
-
+ 35
Max
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,6,10
1,2,3,6,10
1,2,3,6,8
1,2,3,11
1,2,3,7
1,2,3,7
Notes
Datasheet
1,2,3
1,2,3
1,2,4
1,2,5
1,2,9
1,2
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