MPC8572EAMC Freescale Semiconductor, MPC8572EAMC Datasheet - Page 37

• Manufacturer Part Number: MPC8572EAMC
• Description: MPC8572 AMC RAPID SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8572EAMC

• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPC8572E

System PLL Ratio LA[29:31]
e500 Core0 PLL
Ratio
e500 Core1 PLL
Ratio
DDR PLL Ratio
Boot ROM location TSEC1_TXD[6:4],TSEC1_TX_ER
5.1.7
The power-on reset configuration of the PowerQUICC™ III family devices uses dedicated input pins that
are sampled during the assertion of reset to configure the processor. The master reset signal is generated
locally on-board from the reset circuitry, controlled by the System CPLD, as shown in
All of the POR configuration signals are handled via System CPLD control. Some of the MPC8572EAMC
signals are changeable via a set of DIP switches, whereas others are physically hard-wired on the board to
minimize board space. Some of these signals have an internal pull-up that selects a default state.
details all POR configuration pins and their specific usage on the MPC8572EAMC board.
Freescale Semiconductor
POR Usage
MPC8572E Power-On Reset Configuration (POR Config)
(cfg_sys_pll[0:2])
LBCTL, LALE, LGPL2
(cfg_core0_pll[0:2])
LWE[0], UART_SOUT[1],
READY_P1
(cfg_core1_pll[0:2])
TSEC_1588_CLK_OUT,
TSEC_1588_PULSE_OUT1,
TSEC_1588_PULSE_OUT2
(cfg_ddr_pll[0:2])
(cfg_rom_loc[0:3])
(Reset Configuration Name)
Table 5-7. MPC8572E POR Configuration DEFAULT Settings
MPC8572EAMC Advanced Mezzanine Card User Guide, Rev. 1.2
Functional Pin
Figure 5-8. MPC8572E POR Configuration
Default
None
None
None
None
Chip
1111
Setting
Board
1111
100
100
100
100
CCB Clock: SYSCLK Ratio =
10:1
E500 Core0: CCB Clock Ratio =
2:1
E500 Core1: CCB Clock Ratio =
2:1
DDR Complex CLK: DDRCLK
Ratio = 10:1
Local Bus GPCM 32-bit ROM
Board Setup Description
MPC8572EAMC Functional Description
Figure
5-8.
DIP Switches
DIP Switches
DIP Switches
DIP Switches
DIP Switches
Table 5-7
Control
Method
5-13