LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 127

• Manufacturer Part Number: LAN9215-MT
• Description: CONTROLLER, ENET, NON-PCI, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9215-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
SMSC
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
LAN9215i
asu
dsu
csh
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
PIO writes are used for all LAN9215i write cycles. PIO writes can be performed using Chip Select
(nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for
the period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
csl
must be extended using wait states to meet the t
DATASHEET
127
MIN
165
32
13
0
0
7
0
TYP
133
Revision 1.93 (12-12-07)
cycle
MAX
minimum.
UNITS
ns
ns
ns
ns
ns
ns
ns