LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 83

• Manufacturer Part Number: LAN9215-MT
• Description: CONTROLLER, ENET, NON-PCI, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9215-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
SMSC
13-12
BITS
11-7
6-5
4
LAN9215i
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
Reserved
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
Notes:
Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note:
This field does not control multiplexing of the SMI port or other MII signals.
There are restrictions on the use of this field. Please refer to
"MII Interface - External MII Switching," on page 43
---------------------------------------------------
[6]
0
0
1
1
This bit does not control the multiplexing of other MII signals.
[5]
0
1
1
0
[13]
[13]
0
0
1
1
0
0
1
1
MII Clock Source
Internal PHY
External MII Port
Clocks Disabled
Internal PHY
[12]
[12]
0
1
0
1
0
1
0
1
DESCRIPTION
DATASHEET
Threshold (DWORDS)
Threshold (DWORDS)
83
020h
040h
080h
100h
012h
018h
020h
028h
for details.
Section 3.11,
TYPE
R/W
R/W
R/W
RO
Revision 1.93 (12-12-07)
DEFAULT
00b
00
0
-