DS90LV031ATM National Semiconductor, DS90LV031ATM Datasheet - Page 6

• Manufacturer Part Number: DS90LV031ATM
• Description: IC, LVDS DIFFERENTIAL LINE DRIVER SOIC16
• Manufacturer: National Semiconductor

Specifications of DS90LV031ATM

• Supply Current: 30mA
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Device Type: Differential Line Receiver
• Esd Hbm: 6kV
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Applications Information
General application guidelines and hints for LVDS drivers and
receivers may be found in the following application notes:
LVDS Owner's Manual (lit #550062-001), AN808, AN1035,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
vironment for the quick edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic differential
impedance of the media is in the range of 100Ω. A termination
resistor of 100Ω should be selected to match the media, and
is located as close to the receiver input pins as possible. The
termination resistor converts the current sourced by the driver
into a voltage that is detected by the receiver. Other configu-
rations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s),
and other impedance discontinuities as well as ground shift-
ing, noise margin limits, and total termination loading must be
taken into account.
The DS90LV031A differential line driver is a balanced current
source design. A current mode driver, generally speaking has
a high output impedance and supplies a constant current for
a range of loads (a voltage mode driver on the other hand
supplies a constant voltage for a range of loads). Current is
switched through the load in one direction to produce a logic
state and in the other direction to produce the other logic state.
The output current is typically 3.5 mA, a minimum of 2.5 mA,
and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to
terminate the signal and to complete the loop as shown in
Figure
The 3.5 mA loop current will develop a differential voltage of
350 mV across the 100Ω termination resistor which the re-
ceiver detects with a 250 mV minimum differential noise
margin neglecting resistive line losses (driven signal minus
receiver threshold (350 mV – 100 mV = 250 mV)). The signal
is centered around +1.2V (Driver Offset, V
ground as shown in
age (V
(V
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases expo-
nentially in most case between 20 MHz–50 MHz. This is due
to the overlap current that flows between the rails of the device
when the internal gates switch. Whereas the current mode
driver switches a fixed current between its output without any
substantial overlap current. This is similar to some ECL and
PECL devices, but without the heavy static I
of the ECL/PECL designs. LVDS requires > 80% less current
than similar PECL devices. AC specifications for the driver
are a tenfold improvement over other existing RS-422 drivers.
The TRI-STATE function allows the driver outputs to be dis-
abled, thus obtaining an even lower power state when the
transmission of data is not required.
The footprint of the DS90LV031A is the same as the industry
standard 26LS31 Quad Differential (RS-422) Driver and is a
step down replacement for the 5V DS90C031 Quad Driver.
OD
Figure
) and is typically 700 mV.
SS
7. AC or unterminated configurations are not allowed.
) peak-to-peak swing is twice the differential voltage
7. This configuration provides a clean signaling en-
Figure
6. Note that the steady-state volt-
OS
CC
) with respect to
requirements
6
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. High fre-
quency ceramic (surface mount is recommended) 0.1µF in
parallel with 0.01µF, in parallel with 0.001µF at the power
supply pin as well as scattered capacitors over the printed
circuit board. Multiple vias should be used to connect the de-
coupling capacitors to the power planes. A 10µF (35V) or
greater solid tantalum capacitor should be connected at the
power entry point on the printed circuit board.
PC Board considerations:
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a pow-
er/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
Use controlled impedance traces which match the differential
impedance of your transmission medium (ie. cable) and ter-
mination resistor. Run the differential pair trace lines as close
together as possible as soon as they leave the IC (stubs
should be < 10mm long). This will help eliminate reflections
and ensure noise is coupled as common-mode. Lab experi-
ments show that differential signals which are 1mm apart
radiate far less noise than traces 3mm apart since magnetic
field cancellation is greater with the closer traces. Plus, noise
induced on the differential lines is much more likely to appear
as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference
between signals which destroys the magnetic field cancella-
tion benefits of differential signals and EMI will result. (Note
the velocity of propagation, v = c/Er where c (the speed of
light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on
the auto-route function for differential traces. Carefully review
dimensions to match differential impedance and provide iso-
lation for the differential lines. Minimize the number of vias
and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use
arcs or 45° bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
Use a resistor which best matches the differential impedance
of your transmission line. The resistor should be between
90Ω and 130Ω. Remember that the current mode outputs
need the termination resistor to generate the differential volt-
age. LVDS will not work without resistor termination. Typical-
ly, connect a single resistor across the pair at the receiver end.
Surface mount 1% to 2% resistors are best. PCB stubs, com-
ponent lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10mm
(12mm MAX).