EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 29

IC PLD EEPROM 160 MACROCELL 10NS QFP-160

EPM7160SQC160-10N

Manufacturer Part Number
EPM7160SQC160-10N
Description
IC PLD EEPROM 160 MACROCELL 10NS QFP-160
Manufacturer
Altera
Series
MAX 7000Sr
Datasheet

Specifications of EPM7160SQC160-10N

Cpld Type
EEPROM
No. Of Macrocells
160
No. Of I/o's
104
Propagation Delay
10ns
Global Clock Setup Time
3.4ns
Frequency
149.3MHz
Supply Voltage Range
4.75V To 5.25V
Family Name
MAX 7000S
Memory Type
EEPROM
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
104
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7160SQC160-10N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7160SQC160-10N
Manufacturer:
ALTERA
0
Figure 12. MAX 7000 Timing Model
Notes:
(1)
(2)
Altera Corporation
Only available in MAX 7000E and MAX 7000S devices.
Not available in 44-pin devices.
Delay
Input
t
I N
f
Delay
t
PIA
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
relationship of internal and external delay parameters.
For more infomration, see
Timing).
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
(1)
MAX 7000 Programmable Logic Device Family Data Sheet
Expander Delay
Application Note 94 (Understanding MAX 7000
Parallel
t
PEXP
Input Delay
Figure 13
Fast
t
F I N
(1)
Register
t
t
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
shows the internal timing
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
(2)
(2)
(1)
Delay
I/O
t
I O
29

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