EPM7256AEQC208-7N Altera, EPM7256AEQC208-7N Datasheet - Page 18

• Manufacturer Part Number: EPM7256AEQC208-7N
• Description: IC PLD EEPROM 256 MACROCELL 7.5NS QFP208
• Manufacturer: Altera
• Series: MAX 7000AEr

Specifications of EPM7256AEQC208-7N

• Cpld Type: EEPROM
• No. Of Macrocells: 256
• No. Of I/o's: 164
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 3.9ns
• Frequency: 172.4MHz
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX 7000A Programmable Logic Device Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
where: t
t
t
PROG
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle VTCK
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f TCK
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
f
TCK
verify the EEPROM cells
PTCK
Altera Corporation