S29AL016J70TFI010 Spansion Inc., S29AL016J70TFI010 Datasheet
S29AL016J70TFI010
Specifications of S29AL016J70TFI010
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S29AL016J70TFI010 Summary of contents
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... Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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... Publication Number S29AL016J_00 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur ...
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General Description The S29AL016J Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48- pin TSOP ...
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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 3.1 48-pin Standard TSOP (TS048 ...
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Tables Table 7.1 S29AL016J Device Bus Operations ...
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Product Selector Guide Family Part Number Speed Option Max access time ACC Max CE# access time Max CE# access time Note See AC Characteristics on page 44 2. Block Diagram RY/BY ...
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Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 6 A10 A19 WE# 11 RESET WP# 14 RY/BY A18 A17 ...
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February 18, 2010 S29AL016J_00_10 Figure 3.3 64-ball Fortified BGA (Top View, Balls Facing Down A13 ...
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DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 NC DQ7 NC DQ15/A-1 NC VSS BYTE# A16 A15 A14 A13 NC A12 NC A11 A10 A19 WE# REST# 3.1 Special Handling Instructions Special handling is required for Flash Memory products ...
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Pin Configuration A0–A19 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# WP# RESET# RY/BY Logic Symbol February 18, 2010 S29AL016J_00_10 addresses 15 data inputs/outputs DQ15 ...
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Ordering Information 6.1 S29AL016J Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL016J ...
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Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Device Number Speed Option S29AL016J Notes ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of ...
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The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 30 timing specifications and to on page ...
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Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses ...
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Sector A19 A18 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 SA8 0 1 SA9 0 1 SA10 0 1 SA11 0 1 SA12 ...
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Sector A19 A18 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 SA8 0 0 SA9 0 0 SA10 0 0 SA11 0 1 SA12 ...
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Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its ...
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Table 7.7 S29AL016J Top Boot Device Sector/Sector Group Protection Sector / Sector Block SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA29 SA30 SA31 SA32 SA33 SA34 Table 7.8 S29AL016J Bottom Boot Device Sector/Sector Group Protection Sector / Sector Block SA0 ...
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Notes 1. All protected sector unprotected. (If WP bottom two address sectors remains protected for boot sector devices). 2. All previously protected sector groups are protected once again. February 18, 2010 S29AL016J_00_10 ...
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Figure 7.2 In-System Sector Group Protect/Unprotect Algorithms START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Group Unprotect Mode Yes Set up sector group address Sector Group Protect: Write 60h to ...
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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit ...
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The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified ...
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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, ...
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Addresses Addresses (Word Mode) (Byte Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses Addresses (Word Mode) (Byte Mode) 40h 41h 42h 43h 44h 45h ...
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Addresses Addresses (Word Mode) (Byte Mode) 4Fh 50h 9.1 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to hardware data protection measures prevent accidental erasure or programming, ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 10.1 on page 35 address and data values or writing them in the improper sequence resets the device to reading array ...
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Enter/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured ...
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Note See Table 10.1 on page 35 10.7 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock ...
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Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...
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DQ6 status bits, just as in the standard program operation. See information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within ...
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Command Definitions Table Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Group ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 11.1 on page 40 RY/BY#, and DQ6 each offer a method for determining whether a ...
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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at ...
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Reading Toggle Bits DQ6/DQ2 Refer to Figure 11.2 on page 39 toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle ...
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Absolute Maximum Ratings Parameter Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground V (Note 1) CC A9, OE#, and RESET# All other pins (Note 1) Output Short Circuit Current Notes 1. Minimum DC ...
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DC Characteristics 14.1 CMOS Compatible Parameter Input Load Current I LI WP# Input Load Current I A9 Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Note 1) V Active Erase/Program Current ...
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Test Conditions Note Diodes are IN3064 or equivalent. Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 16. Key to Switching ...
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AC Characteristics 17.1 Read Operations Parameter JEDEC Std t t AVAV AVQV ACC t t ELQV GLQV EHQZ GHQZ DF t SR/W t OEH t t AXQX ...
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Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms READY Read or Write RESET# Pin Low (NOT During Embedded Algorithms READY Read or Write t RESET# Pulse Width RP t RESET# High ...
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Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# BYTE# DQ0–DQ14 ...
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Erase/Program Operations Parameter JEDEC Std t t AVAV AVWL WLAX DVWH WHDX DH t OES t t GHWL GHWL t t ELWL WHEH CH ...
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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see 2. Illustration shows device in word mode. Addresses CE# OE# WE# t ...
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Addresses CE OE# WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE# t OE# WE# DQ6/DQ2 t ...
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Figure 17.10 DQ2 vs. DQ6 for Erase and Erase Suspend Operations Enter Embedded Erasing WE# DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an ...
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Temporary Sector Group Unprotect Parameter JEDEC Std t VIDR t RSP t RRB Note Not 100% tested. 12V RESET CE# WE# RY/BY RESET# SA, A6, A3, A2 A1, A0 Data CE# WE# ...
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Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t AVAV AVEL ELAX DVEH EHDX DH t OES t t GHEL GHEL t t WLEL WS t ...
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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Note 3) Notes 1. Typical program and erase times assume the following conditions Under worst case conditions ...
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Physical Dimensions 20.1 TS 048—48-Pin Standard TSOP PACKAGE JEDEC SYMBOL MIN A --- A1 0.05 A2 0.95 b1 0.17 b 0.17 c1 0.10 c 0.10 D 19.80 D1 18.30 E 11. 0.50 Θ 0˚ R 0.08 N ...
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VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA) 8. 6.15 mm INDEX MARK PIN A1 CORNER PACKAGE VBK 048 JEDEC 8. 6.15 mm NOM PACKAGE SYMBOL MIN A --- A1 0.18 A2 0.62 D ...
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LAE064–64-Ball Fortified Ball Grid Array (BGA PACKAGE LAE 064 JEDEC N/A 9. 9.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 PROFILE HEIGHT A1 0.40 --- --- STANDOFF A2 0.60 ...
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SSOP56- 56-Pin Shrink Small Outline Package PACKAGE JEDEC MO-180 (A) BA SYMBOL MIN A --- A1 0.45 A2 1.15 b *0.25 b1 0.30 c 0.10 c1 0.10 D 23.40 E 15.70 E1 13.10 e 0.80 BASIC L 0.60 R ...
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Revision History Section Revision 01 (April 10, 2007) Initial release. Revision 02 (May 17, 2007) Global Deleted references to ACC input. General Description Corrected ball count for Fortified BGA package. Product Selector Guide Changed maximum t Autoselect Codes (High ...
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Section Revision 06 (August 12, 2008) Title changed to Sector Group Protection and Unprotection Sector Protection/Unprotection Section amended and restated to Sector Group Protection and Unprotection Title changed to Temporary Sector Group Unprotect Figure 7.2; Title changed to Temporary Sector ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007-2010 Spansion Inc. All rights reserved. Spansion EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. ...