Flash 3V 32Mb Float Gate two address 90s

S29GL032N90TFI030

Manufacturer Part NumberS29GL032N90TFI030
DescriptionFlash 3V 32Mb Float Gate two address 90s
ManufacturerSpansion Inc.
S29GL032N90TFI030 datasheet
 


Specifications of S29GL032N90TFI030

Memory TypeNORMemory Size32 Mbit
Access Time90 nsData Bus Width8 bit, 16 bit
ArchitectureUniform / Boot SectorInterface TypePage-mode
Supply Voltage (max)3.6 VSupply Voltage (min)2.7 V
Maximum Operating Current50 mAMounting StyleSMD/SMT
Operating Temperature+ 85 CPackage / CaseTSOP-48
Ic Interface TypeCFI, ParallelSupply Voltage Range2.7V To 3.6V
Memory Case StyleTSOPNo. Of Pins48
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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S29GL-N MirrorBit
S29GL064N, S29GL032N
64 Megabit, 32 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 110 nm MirrorBit Process Technology
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Publication Number S29GL-N_01
®
Flash Family
Notice On Data Sheet Designations
Revision 12
Issue Date October 29, 2008
S29GL-N MirrorBit
®
Flash Family Cover Sheet
for definitions.

S29GL032N90TFI030 Summary of contents

  • Page 1

    ... S29GL-N MirrorBit S29GL064N, S29GL032N 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production ...

  • Page 2

    ... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

  • Page 3

    ... S29GL-N MirrorBit S29GL064N, S29GL032N 64 Megabit, 32 Megabit 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation Manufactured on 110 nm MirrorBit process technology Secured Silicon Sector region – 128-word/256-byte sector for permanent, secure identification ...

  • Page 4

    ... The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses are stable for a specified period of time ...

  • Page 5

    ... Password Sector Protection 8.13 Password and Password Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.14 Persistent Protection Bit Lock (PPB Lock Bit 8.15 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.16 Write Protect (WP#/ACC 8.17 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. Common Flash Memory Interface (CFI ...

  • Page 6

    Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    Figures Figure 3.1 48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 8

    Tables Table 6.1 S29GL032N Ordering Options Table 8.1 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 9

    Product Selector Guide Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (ns) Max. OE# Access Time (ns) 2. Block Diagram RY/BY RESET# WE# State Control WP#/ACC ...

  • Page 10

    ... Connection Diagrams Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A15 A14 A13 A12 ...

  • Page 11

    October 29, 2008 S29GL-N_01_12 Figure 3.3 64-ball Fortified BGA S29GL064N, S29GL032N (Models 01, 02, 03, 04, V1, V2 only) Top View, Balls Facing Down NC on S29GL032N ...

  • Page 12

    A6 A13 WE# A3 RY/BY Figure 3.4 48-ball Fine-pitch BGA (VBK 048) S29GL064N, S29GL032N (Models 03, 04 only) Top View, Balls Facing Down ...

  • Page 13

    Pin Descriptions Pin A21–A0 A20–A0 DQ7–DQ0 DQ14–DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC ACC WP# RESET# RY/BY# BYTE October 29, 2008 S29GL-N_01_12 Description 22 ...

  • Page 14

    Logic Symbols Figure 5.1 S29GL064N Logic Symbol (Models 01, 02, V1, V2) 22 A21–A0 DQ15–DQ0 CE# OE# WE# WP#/ACC RESET# V RY/BY# IO BYTE# Figure 5.3 S29GL064N Logic Symbol (Models 06, 07, V6, V7) 22 A21–A0 DQ15–DQ0 CE# OE# ...

  • Page 15

    ... PACKAGE TYPE Fortified Ball-Grid Array Package(LAE064 SPEED OPTION See Product Selector Guide and Valid Combinations ( ns 110 ns) DEVICE NUMBER/DESCRIPTION S29GL032N 32 Megabit Page-Mode Flash Memory Manufactured using 110 nm MirrorBit Table 6.1 S29GL032N Ordering Options S29GL032N Valid Combinations Device Speed Package, Material, Number Option & ...

  • Page 16

    ... F = Fortified Ball-Grid Array Package (LAA064 Thin Small Outline Package (TSOP) Standard Pinout SPEED OPTION See Product Selector Guide and Valid Combinations ( ns 110 ns) DEVICE NUMBER/DESCRIPTION S29GL064N, 64 Megabit Page-Mode Flash Memory Manufactured using 110 nm MirrorBit 7.1 Valid Combinations Speed Device Number Option S29GL064N Notes 1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3 ...

  • Page 17

    ... The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE WE# must remain at V DQ15-DQ0 after address access time (t data ...

  • Page 18

    ... Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings (t Autoselect Command Sequence on page 42 ...

  • Page 19

    ... CMOS standby current (I The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to diagram ...

  • Page 20

    Table 8.2 S29GL032N (Models 01, 02, V1, V2) Sector Addresses Sector Size 8-bit (KB/ Address Sector A20-A15 Kwords) Range SA0 000000 64/32 000000h–00FFFFh SA1 000001 64/32 010000h–01FFFFh SA2 000010 64/32 020000h–02FFFFh SA3 000011 64/32 030000h–03FFFFh SA4 000100 64/32 040000h–04FFFFh SA5 ...

  • Page 21

    Table 8.3 S29GL032N (Model 03) Top Boot Sector Addresses Sector Size 8-bit (KB/ Address Sector A20–A12 Kwords) Range SA0 000000xxx 64/32 000000h–00FFFFh SA1 000001xxx 64/32 010000h–01FFFFh SA2 000010xxx 64/32 020000h–02FFFFh SA3 000011xxx 64/32 030000h–03FFFFh SA4 000100xxx 64/32 040000h–04FFFFh SA5 000101xxx ...

  • Page 22

    Table 8.4 S29GL032N (Model 04) Bottom Boot Sector Addresses Sector Size 8-bit (KB/ Address Sector A20–A12 Kwords) Range SA0 000000000 8/4 000000h–001FFFh SA1 000000001 8/4 002000h–003FFFh SA2 000000010 8/4 004000h–005FFFh SA3 000000011 8/4 006000h–007FFFh SA4 000000100 8/4 008000h–009FFFh SA5 000000101 ...

  • Page 23

    Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A15 Kwords) Range SA0 0000000 64/32 000000h–00FFFFh SA1 0000001 64/32 010000h–01FFFFh SA2 0000010 64/32 020000h–02FFFFh SA3 0000011 64/32 030000h–03FFFFh SA4 ...

  • Page 24

    Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A15 Kwords) Range SA46 0101110 64/32 2E0000h–2EFFFFh SA47 0101111 64/32 2F0000h–2FFFFFh SA48 0110000 64/32 300000h–30FFFFh SA49 0110001 64/32 310000h–31FFFFh SA50 ...

  • Page 25

    Table 8.6 S29GL064N (Model 03) Top Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA23 0010111xxx 64/32 170000h–17FFFFh SA24 0011000xxx 64/32 180000h–18FFFFh SA25 0011001xxx 64/32 190000h–19FFFFh SA26 0011010xxx 64/32 1A0000h–1AFFFFh SA27 0011011xxx ...

  • Page 26

    Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA0 0000000000 8/4 000000h–001FFFh SA1 0000000001 8/4 002000h–003FFFh SA2 0000000010 8/4 004000h–005FFFh SA3 0000000011 8/4 006000h–007FFFh SA4 0000000100 ...

  • Page 27

    Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet Sector Size 8-bit (KB/ Address Sector A21–A12 Kwords) Range SA91 1010100xxx 64/32 540000h–54FFFFh SA92 1010101xxx 64/32 550000h–55FFFFh SA93 1010110xxx 64/32 560000h–56FFFFh SA94 1010111xxx 64/32 570000h–57FFFFh SA95 1011000xxx ...

  • Page 28

    Table 8.8 S29GL064N (Models 06, 07, V6, V7) Sector Addresses (Sheet Sector A21–A15 SA19 0010011 SA20 0010100 SA21 0010101 SA22 0010110 SA23 0010111 SA24 0011000 SA25 0011001 SA26 0011010 SA27 0011011 SA28 0011100 SA29 0011101 SA30 0011110 ...

  • Page 29

    Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding ...

  • Page 30

    Advanced Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors: 8.9.1 Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled ...

  • Page 31

    Lock Register The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of ...

  • Page 32

    ... PPB erasing. All PPB bits erase in parallel, unlike programming where individual PPB bits are programmable. The PPB bits are limited to the same number of cycles as a flash memory sector. Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer. ...

  • Page 33

    Persistent Protection Bit Lock (PPB Lock Bit) A global volatile bit. When set to the “freeze state”, the PPB bits cannot be changed. When cleared to the “unfreeze state”, the PPB bits are changeable. There is only one PPB ...

  • Page 34

    ... Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Password Read commands. The password function works in conjunction with the Password Protection Mode Lock Bit, which when programmed, prevents the Password Read command from reading the contents of the password on the pins of the device ...

  • Page 35

    ... Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory ...

  • Page 36

    ... Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command ...

  • Page 37

    ... IL edge of WE#. The internal state machine is automatically reset to the read mode on power-up. 9. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices ...

  • Page 38

    Addresses (x16) Addresses (x8) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Note CFI data related to V and time-outs may differ from actual V CC tables to obtain the V range for particular part numbers. ...

  • Page 39

    Addresses (x16) Addresses (x8) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch October 29, 2008 S29GL-N_01_12 Table ...

  • Page 40

    Addresses (x16) Addresses (x8) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h Table 9.4 Primary Vendor-Specific Extended Query Data Description 80h ...

  • Page 41

    Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 10.1 on page 51 Writing incorrect address and data values or writing them in the improper sequence may place the device ...

  • Page 42

    ... Identifier Code Manufacturer ID show the address and data requirements for both command Secured Silicon Sector Flash Memory Region on page 35 Table 10.1 on page 51 and Table 10.3 on page 53 ® S29GL-N MirrorBit Flash Family A7:A0 ...

  • Page 43

    Any bit in a word cannot be programmed from 0 back Attempting may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a ...

  • Page 44

    Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load ...

  • Page 45

    Notes 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, ...

  • Page 46

    Note See Table 10.1 on page 51 10.5 Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any ...

  • Page 47

    ... Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. ...

  • Page 48

    ... Table 10.3 on page 53 The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. ...

  • Page 49

    Notes 1. See Table 10.1 and Table 10.3 2. See the section on DQ3 for information on the sector erase timer. October 29, 2008 S29GL-N_01_12 Figure 10.4 Erase Operation START Write ...

  • Page 50

    Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during ...

  • Page 51

    ... CFI Query (Note 17) 1 Legend X = Don’t care RA = Read Address of memory location to be read Read Data read from location RA during read operation Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. Notes 1. See Table 8.1 on page 17 for description of bus operations ...

  • Page 52

    ... SA Command Set Exit 2 XX (Note 7) Legend X = Don’t care Address of the memory location to be read Sector Address. Any address that falls within a specified sector. See Tables 8.2–8.8 for sector address ranges. Notes 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. ...

  • Page 53

    ... CFI Query (Note 16) 1 Legend X = Don’t care RA = Read Address of memory location to be read Read Data read from location RA during read operation Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. Notes 1. See Table 8.1 on page 17 for description of bus operations ...

  • Page 54

    ... SA Command Set Exit 2 XXX (Note 7) Legend X = Don’t care Address of the memory location to be read Sector Address. Any address that falls within a specified sector. See Tables 8.2–8.8 for sector address ranges. Notes 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. ...

  • Page 55

    Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 10.5 on page 60 and DQ6 each offer a method for determining whether a ...

  • Page 56

    Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...

  • Page 57

    DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any ...

  • Page 58

    Note The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information. 10.14 DQ2: Toggle Bit II ...

  • Page 59

    Figure 10.6 on page 58 toggle bit timing diagram. form. 10.15 Reading Toggle Bits DQ6/DQ2 Refer to Figure 10.6 on page 58 toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle ...

  • Page 60

    DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer on page ...

  • Page 61

    Absolute Maximum Ratings Storage Temperature, Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground Output Short Circuit Current Notes 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os ...

  • Page 62

    DC Characteristics Table 13.1 DC Characteristics, CMOS Compatible Parameter Symbol Parameter Description (Notes) I Input Load Current (Note Input Load Current LIT I Output Leakage Current Initial Read Current (Note 1) CC1 ...

  • Page 63

    Test Conditions Note Diodes are IN3064 or equivalent. Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 14.1 Key to Switching ...

  • Page 64

    AC Characteristics Parameter JEDEC Std Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t t Output ...

  • Page 65

    Addresses CE# OE# WE# Outputs RESET# RY/BY A23-A2 A1-A0* Data Bus CE# OE# Note * Figure shows device in word mode. Addresses are A1–A-1 for byte mode. October 29, 2008 S29GL-N_01_12 ...

  • Page 66

    Parameter JEDEC Std. t RESET# Pin Low (During Embedded Algorithms) to Read Mode Ready RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode t Ready (See Note) t RESET# Pulse Width RP t Reset High Time Before Read RH ...

  • Page 67

    Parameter JEDEC Std Write Cycle Time AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t Address Hold Time WLAX AH t Address Hold Time ...

  • Page 68

    Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word mode. V ...

  • Page 69

    Figure 15.7 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase), VA ...

  • Page 70

    Figure 15.9 Toggle Bit Timings (During Embedded Algorithms) Addresses CE# t OEH WE# OE Valid Data DQ6 / DQ2 RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, ...

  • Page 71

    Table 15.4 Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup Time DVEH DS ...

  • Page 72

    Figure 15.11 Alternate CE# Controlled Write (Erase/Program) Operation Timings Addresses WE# OE# CE# Data t RESET# RY/BY# Notes 1. Figure indicates last two bus cycles of a program or erase operation program address sector address, ...

  • Page 73

    Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Total Write Buffer Program Time (Notes 3, 5) Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) Chip Program Time Notes 1. Typical program and erase times ...

  • Page 74

    Physical Dimensions 17.1 TS048—48-Pin Standard Thin Small Outline Package (TSOP) STANDARD PIN OUT (TOP VIEW SEE DETAIL B SEE DETAIL B - SEE DETAIL A SEE DETAIL A R 0˚ PARALLEL ...

  • Page 75

    TS056—56-Pin Standard Thin Small Outline Package (TSOP) STANDARD PIN OUT (TOP VIEW SEE DETAIL 0. (N/2 TIPS) B SEE DETAIL A θ° PARALLEL TO SEATING PLANE DETAIL ...

  • Page 76

    VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package D INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 8. 6.15 mm NOM PACKAGE SYMBOL MIN ...

  • Page 77

    LAA064—64-Ball Fortified Ball Grid Array (BGA Package PACKAGE LAA 064 JEDEC N/A 13. 11.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 A1 0.40 --- --- A2 0.60 --- --- D ...

  • Page 78

    LAE064-64-Ball Fortified Ball Grid Array (BGA Package PACKAGE JEDEC 9. 9.00 mm SYMBOL MIN A --- A1 0. φb 0. ...

  • Page 79

    Revision History Section Revision 01 (February 12, 2007) Initial release. Revision 02 (February 26, 2007) Global Replaced LAE064 package with LAA064. Page Mode Read Corrected bit ranges in first paragraph. Erase And Programming Performance Modified maximum sector erase time ...

  • Page 80

    Section Revision 11 (August 5, 2008) DC Characteristics Changed Note 1 in Table DC Characteristics- CMOS Compatible Ordering Information Added LAE064 package option Connection Diagram Figure 3.3; Title changed to 64ball Fortified BGA Physical Dimensions Added LAE064 package option Revision ...

  • Page 81

    ... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007-2008 Spansion Inc. All rights reserved. Spansion ™ ™ ...