S29GL064A10TFIR20 Spansion Inc., S29GL064A10TFIR20 Datasheet - Page 19

• Manufacturer Part Number: S29GL064A10TFIR20
• Description: Flash - NOR IC
• Manufacturer: Spansion Inc.

Specifications of S29GL064A10TFIR20

• Memory Size: 64Mbit
• Memory Configuration: 64K X 16
• Ic Interface Type: Parallel
• Access Time: 100ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Page/burst Read Access: 25ns
• Supply Voltage Max: 3.6V
• Sector Type: Uniform
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4
8.5
8.6
8.7
November 16, 2007 S29GL-N_01_09
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than V
V
standard access time (t
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to the
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to the
Characteristics on page 62
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
progress, Hi-Z all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to
diagram.
When the OE# input is at V
impedance state.
IO
± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
DC Characteristics on page 62
CE
D a t a
) for read access when the device is in either of these standby modes, before it is
IH
for the automatic sleep mode current specification.
, output from the device is disabled. The output pins are placed in the high
S29GL-N MirrorBit
CC5
). If RESET# is held at V
S h e e t
for the standby current specification.
ACC
®
Flash Family
RP
+ 30 ns. The automatic sleep mode is independent of the
, the device immediately terminates any operation in
IH
.) If CE# and RESET# are held at V
IL
but not within V
Figure 15.4 on page 66
SS
±0.3 V, the standby current is
SS
±0.3 V, the device
IH
, but not within
for the timing
IO
± 0.3 V.
DC
19