H27UF081G1M-TPCB HYNIX SEMICONDUCTOR, H27UF081G1M-TPCB Datasheet
H27UF081G1M-TPCB
Specifications of H27UF081G1M-TPCB
Related parts for H27UF081G1M-TPCB
H27UF081G1M-TPCB Summary of contents
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NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / May. 2007 1Gbit (128Mx8bit ...
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Document Title 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History Revision No. 0.01 Initial Draft. 1) Delete PRE pin. 2) Delete Lock mechanism. 0.02 3) Delete FBGA Package. - Figure & dimension are changed. 1) Change DC characteristics (Table ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - VCC = 2.7 to ...
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SUMMARY DESCRIPTION The HYNIX HY27US(08/16)1G1M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The ...
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IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure1: Logic Diagram Data Inputs / Outputs (x16 Only) Data Inputs ...
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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48USOP1 Contactions, x8 Device Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 6 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...
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IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 4th Cycle A25 NOTE must be set to Low set to LOW or High by the 00h or 01h Command. IO0 1st Cycle A0 2nd ...
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CLE ALE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the four address input cycles. Once the ...
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Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...
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Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...
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OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides ...
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Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles with ECC. (1bit/528bytes) Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient ...
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Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 4: Block Diagram Preliminary 16 ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Leve Output Low Current (R/B) Table 8: DC ...
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Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Number of partial Program Cycles in the same page Block Erase Time Table 11: Program / Erase Characteristics Rev 0.2 / May. 2007 HY27US(08/16)1G1M ...
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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...
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Pagae IO Program 0 Pass / Fail Ready/Busy 6 Ready/Busy 7 Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th Part Number Voltage HY27US081G1M 3.3V HY27US161G1M 3.3V Rev 0.2 / May. ...
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Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 5: Command Latch Cycle Figure 6: Address Latch Cycle Preliminary HY27US(08/16)1G1M Series 21 ...
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CE RE I/Ox R/B Notes : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.2 / May. 2007 1Gbit ...
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CLE I/O x CLE CE tWC WE ALE RE I/O x 00h or 01h Col. Add1 Row Add1 Row Add2 Column Address R/B Figure 10: Read1 Operation (Read One Page) Rev 0.2 / May. 2007 1Gbit (128Mx8bit ...
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Figure 11: Read1 Operation intercepted by CE Figure 12: Read2 Operation (Read One Page) Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 24 ...
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Figure 13: Sequential Row Read Operation Within a Block Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 25 ...
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CLE CE tWC WE ALE RE I/Ox 80h Col. Add1 Serial Data Column Input Command Address R/B Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash tWC tWC Din Row Add1 Row Add2 Row Add3 N Row Address ...
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Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 15 : Copy Back Program Preliminary HY27US(08/16)1G1M Series 27 ...
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Figure 16: Block Erase Operation (Erase One Block) Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 17 : Read ID Operation Preliminary HY27US(08/16)1G1M Series 28 ...
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Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 18 : Automatic Read at Power On Figure 19 : Reset Operation Preliminary HY27US(08/16)1G1M Series 29 ...
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Figure 20: Power On and Data Protection Timing Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash VTH = 2.5 Volt for 3.3 Volt Supply devices Preliminary HY27US(08/16)1G1M Series 30 ...
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Figure 21: Ready/Busy Pin electrical specifications Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 31 ...
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Figure 23: Pointer Operations for porgramming Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 22: Pointer operations Preliminary HY27US(08/16)1G1M Series 32 ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 27~30) Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash ...
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Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 29: Enable Erasing Figure 30: Disable Erasing Preliminary 36 ...
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Figure 31: 48pin-TSOP1 20mm, Package Outline Symbol alpha Table 17: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.2 / May. 2007 1Gbit (128Mx8bit / 64Mx16bit) NAND ...
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Figure 32. 48pin-USOP1 17mm, Package Outline Symbol alpha Table 18: 48pin-USOP1 17mm, Package Mechanical Data Rev 0.2 / May. 2007 HY27US(08/16)1G1M Series 1Gbit (128Mx8bit / ...
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MARKING INFORMATION - ...