AM29F800BT-55SF Spansion Inc., AM29F800BT-55SF Datasheet - Page 5

• Manufacturer Part Number: AM29F800BT-55SF
• Description: IC, FLASH, 8MBIT, 55NS, SOIC-44
• Manufacturer: Spansion Inc.

Specifications of AM29F800BT-55SF

• Memory Type: Flash
• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Access Time: 55ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 23
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 23
November 2, 2006 21504E5
Special Handling Instructions for FBGA Package .................... 6
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Autoselect Mode ..................................................................... 12
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Hardware Data Protection ...................................................... 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 15
Word/Byte Program Command Sequence ............................. 15
Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 16
Command Definitions ............................................................. 18
DQ7: Data# Polling ................................................................. 19
RY/BY#: Ready/Busy# ........................................................... 20
DQ6: Toggle Bit I .................................................................... 20
DQ2: Toggle Bit II ................................................................... 20
Reading Toggle Bits DQ6/DQ2 .............................................. 20
DQ5: Exceeded Timing Limits ................................................ 21
DQ3: Sector Erase Timer ....................................................... 21
Table 1. Am29F800B Device Bus Operations ..................................9
Table 2. Am29F800BT Top Boot Block Sector Address Table .......11
Table 3. Am29F800BB Bottom Boot Block Sector Address Table ..12
Table 4. Am29F800B Autoselect Codes (High Voltage Method) ....13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Figure 2. Program Operation .......................................................... 15
Figure 3. Erase Operation............................................................... 17
Table 5. Am29F800B Command Definitions ...................................18
Figure 4. Data# Polling Algorithm ................................................... 19
Figure 5. Toggle Bit Algorithm......................................................... 21
Table 6. Write Operation Status ......................................................22
Figure 6. Maximum Negative Overshoot Waveform ....................... 23
Figure 7. Maximum Positive Overshoot Waveform......................... 23
D A T A S H E E T
Am29F800B
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase and Programming Performance . . . . . . . 37
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 37
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41
TTL/NMOS Compatible .......................................................... 24
CMOS Compatible .................................................................. 25
Read Operations .................................................................... 27
Hardware Reset (RESET#) .................................................... 28
Word/Byte Configuration (BYTE#) ........................................ 29
Erase/Program Operations ..................................................... 30
Temporary Sector Unprotect .................................................. 34
SO 044—44-Pin Small Outline Package ................................ 38
TS 048—48-Pin Standard Pinout Thin Small
Outline Package (TSOP) ........................................................ 39
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
package .................................................................................. 40
Revision A (August 1997) ....................................................... 41
Revision B (October 1997) ..................................................... 41
Revision C (January 1998) ..................................................... 41
Revision C+1 (April 1998) ....................................................... 41
Revision C+2 (April 1998) ....................................................... 41
Revision D (January 1999) ..................................................... 42
Revision D+1 (March 23, 1999) .............................................. 42
Revision D+2 (July 2, 1999) ................................................... 42
Revision E (November 16, 1999) ............................................ 42
Revision E+1 (August 4, 2000) ............................................... 42
Revision E+2 (June 4, 2004) .................................................. 42
Revision E3 (December 22, 2005) .......................................... 42
Revision E4 (May 19, 2006) ................................................... 42
Revision E5 (November 2, 2006) ............................................ 42
Figure 8. Test Setup....................................................................... 26
Table 7. Test Specifications ........................................................... 26
Figure 9. Read Operations Timings ............................................... 27
Figure 10. RESET# Timings .......................................................... 28
Figure 11. BYTE# Timings for Read Operations............................ 29
Figure 12. BYTE# Timings for Write Operations............................ 29
Figure 13. Program Operation Timings.......................................... 31
Figure 14. Chip/Sector Erase Operation Timings .......................... 32
Figure 15. Data# Polling Timings (During Embedded Algorithms). 33
Figure 16. Toggle Bit Timings (During Embedded Algorithms)...... 33
Figure 17. DQ2 vs. DQ6................................................................. 34
Figure 18. Temporary Sector Unprotect Timing Diagram .............. 34
Figure 19. Alternate CE# Controlled Write Operation Timings ...... 36
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