UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 445

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
Address: FF48H
Symbol
EGP
Address: FF49H
Symbol
EGN
These registers specify the valid edge for INTP0 to INTP3.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Table 17-3 shows the ports corresponding to EGPn and EGNn.
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
Remark n = 0 to 3
EGPn
Detection Enable Register
7
0
7
0
0
0
1
1
After reset: 00H
After reset: 00H
Figure 17-5. Format of External Interrupt Rising Edge Enable Register (EGP)
EGP0
EGP1
EGP2
EGP3
detected when the external interrupt function is switched to the port function.
EGNn
6
0
6
0
0
1
0
1
Table 17-3. Ports Corresponding to EGPn and EGNn
and External Interrupt Falling Edge Enable Register (EGN)
EGN1
EGN3
EGN0
EGN2
R/W
R/W
Edge detection disabled
Falling edge
Rising edge
Both rising and falling edges
CHAPTER 17 INTERRUPT FUNCTIONS
5
0
5
0
P120/EXLVI
P34/TI52/TI010/TO00/RTC1HZ
P33/TI000/RTCDIV/RTCCL/BUZ
P31/TOH1
User’s Manual U18698EJ1V0UD
Edge Detection Port
INTPn pin valid edge selection (n = 0 to 3)
4
0
4
0
EGN3
EGP3
3
3
EGP2
EGN2
2
2
INTP0
INTP1
INTP2
INTP3
Interrupt Request Signal
EGP1
EGN1
1
1
EGP0
EGN0
0
0
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