ADC12D040CIVS National Semiconductor, ADC12D040CIVS Datasheet - Page 16

• Manufacturer Part Number: ADC12D040CIVS
• Description: DUAL 12BIT ADC, 40MSPS, SMD, 12D040
• Manufacturer: National Semiconductor

Specifications of ADC12D040CIVS

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analogue: 4.75V To 5.25V
• Supply Voltage Range - Digital: 2.35V To 5.25V, 4.75V To 5.25V
• Sampling Rate: 40MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
Operating on a single +5V supply, the ADC12D040 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 12 bits. The reference input is buffered
to ease the task of driving that pin.
The output word rate is the same as the clock frequency,
which can be between 100 kSPS and 55 MSPS (typical).
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by
the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 75 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12D040:
1.1 Analog Inputs
The ADC12D040 has two analog signal inputs, V
V
one reference input pin, V
The analog input circuitry contains an input boost circuit that
provides improved linearity over a wide range of analog input
voltages. To prevent an on-chip over voltage condition that
could impair device reliability, the input signal should never
exceed the voltage described as
1.2 Reference Pins
The ADC12D040 is designed to operate with a 2.0V refer-
ence, but performs well with reference voltages in the range
of 1.0V to 2.4V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12D040. Increasing
the reference voltage (and the input signal swing) beyond
2.4V may degrade THD for a full-scale input especially at
higher input frequencies. It is important that all grounds
associated with the reference voltage and the input signal
make connection to the analog ground plane at a single point
in that plane to minimize the effects of noise currents in the
ground path.
The ADC12040 will perform well with reference voltages up
to 2.4V for full-scale input frequencies up to 10 MHz. How-
ever, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The six Reference Bypass Pins (V
V
These pins should each be bypassed to ground with a 0.1 µF
capacitor. Smaller capacitor values will allow faster recovery
from the power down mode, but may result in degraded
noise performance. DO NOT LOAD these pins. Loading any
of these pins may result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
IN
RM
4.75V ≤ V
V
2.35V ≤ V
V
100 kHz ≤ f
1.0V ≤ V
−. These two pins form a differential input pair. There is
D
REF
B and V
= V
/2 ≤ V
A
REF
A
DR
RN
CM
CLK
≤ 5.25V
B) are made available for bypass purposes.
≤ 2.4V
≤ V
≤ V
≤ 55 MHz
D
A
- V
V
A
REF
REF
- V
.
REF
/2.
RP
A, V
RM
A, V
RN
A, V
IN
+ and
RP
B,
16
The V
source (V
current is drawn from it. However, because the voltages at
these pins are half that of the V
for a common mode source will result in reduced input
headroom (the difference between the V
and the peak signal voltage at either analog input) and the
possibility of reduced THD and SFDR performance. For this
reason, it is recommended that V
least 2 Volts. For high input frequencies it may be necessary
to increase this headroom to maintain THD and SFDR per-
formance.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
main between ground and 4V.
The Peaks of the individual input signals (V
should each never exceed the voltage described as
to maintain THD and SINAD performance.
The ADC12D040 performs best with a differential input with
each input centered around a common V
peak voltage swing at both V
the value of the reference voltage or the output data will be
clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For a complex waveform, however,
angular errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
V
V
V
RM
RP
RN
A = V
A = V
A = V
RM
V
IN
FIGURE 2. Expected Input Signal Range
+, V
CM
pins may be used as a common mode voltage
RP
RN
RM
) for the analog input pins as long as no d.c.
IN
B = V
B = V
B = V
− = (V
V
RM
RM
A
IN
REF
/ 2
IN
E
= (V
+ V
− V
+ and V
FS
/2 + V
A
REF
REF
IN
/2. The input signals should re-
= dev
IN
+) – (V
+ and V
A
/ 2
/ 2
CM
supply pin, using these pins
IN
A
1.79
−. The input signal, V
always exceed V
) ≤ 4V (differential)
IN
IN
−)
− should not exceed
20046011
A
CM
supply voltage
. The peak-to-
IN
+ and V
REF
by at
IN
IN
, is
−)