HY27UF084G2B-TPCB HYNIX SEMICONDUCTOR, HY27UF084G2B-TPCB Datasheet
HY27UF084G2B-TPCB
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HY27UF084G2B-TPCB Summary of contents
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NAND FLASH HY27UF(08/16)4G2B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B ...
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Document Title 4Gbit (512Mx8bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Correct Cache Read 2) Correct Valid Bad Block Numbers 0.1 3) Delete ULGA package 4) Correct Read ID - 3th cycle : 50h → 10h ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications MULTIPLANE ARCHITECTURE - Array is split into two independent planes. Parallel Operations on both planes are available, halving Program and erase time. NAND INTERFACE - ...
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DESCRIPTION Hynix NAND HY27UF(08/16)4G2B Series have 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid ...
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IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 only) Data Input / Outputs ...
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Figure 2. 48TSOP1 Contact, x8 and x16 Device Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 6 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program (1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...
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IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE must be set to Low. IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 5th Cycle A27 NOTE must be ...
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CLE ALE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable ...
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DEVICE OPERATION 3.1 Page Read. This operation is operated by writing 00h and 30h to the command register along with five address cycles. Two types of operations are available: random read, serial page read. The random read mode is ...
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Multi Plane Program. Device supports multiple plane program possible to program in parallel 2 pages, one per each plane. A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes ...
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Copy-back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, ...
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EDC Operation Error Detection Code check automatically starts immediately after device becomes busy for a copy back program oper- ation (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 ...
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Cache Read Cache read operation allows automatic download of consecutive pages. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page start (A<10:0>=00h), ...
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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides ...
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Parameter Symbol Valid Block NVB Number NOTE: 1. The 1st block is guaranteed valid block at the time of shipment. Symbol Ambient Operating Temperature (Commercial Temperature Range Ambient Operating Temperature (Industrial Temperature Range) T Temperature ...
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Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash Figure 3: Block Diagram 18 ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Table 9: DC ...
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Item Input / Output Capacitance Input Capacitance Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time / Multi-Plane Program Time Dummy Busy Time for Two Plane Program Number of partial Program Cycles in the same page Block Erase Time / ...
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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...
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... Pass / Fail Ready / Busy 6 Ready / Busy 7 Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th 5th Part Number Voltage HY27UF084G2B 3.3V HY27UF164G2B 3.3V Rev 0.4 / Jan. 2008 Block Erase Read Pass / Fail Ready / Ready / Busy Busy Ready / Ready / Busy Busy Write ...
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Description 1 2 Die / Package Level Cell 4 Level Cell Cell Type 8 Level Cell 16 Level Cell 1 Number of 2 Simultaneously 4 Programmed Pages 8 Interleave Program Not Between multiple chips Supported Not Write ...
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Description 1 2 Plane Number 4 8 64Mb 128Mb 256Mb 512Mb Plane Size (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved Table 19: 5rd Byte of Device Idendifier Description Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash ...
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Table 20: Page organization in EDC units (x8) Table 21: Page organization in EDC units (x16 Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Copy back Program Pass/Fail EDC status ...
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Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 4: Command Latch Cycle Figure 5: Address Latch Cycle HY27UF(08/16)4G2B Series 26 ...
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Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 6: Input Data Latch Cycle HY27UF(08/16)4G2B Series 27 ...
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Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 8: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 28 ...
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Figure 10: Read1 Operation (Read One Page) Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 9: Status Read Cycle HY27UF(08/16)4G2B Series 29 ...
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Figure 11: Read1 Operation intercepted by CE Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 30 ...
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Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 12: Random Data output HY27UF(08/16)4G2B Series 31 ...
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Figure 13: Read Operation with Read Cache Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 1 32 ...
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Rev 0.4 / Jan. 2008 Figure 14: Page Program Operation HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 33 ...
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Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 15: Random Data In HY27UF(08/16)4G2B Series 34 ...
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Rev 0.4 / Jan. 2008 Figure 16: Copy Back Program Operation HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 35 ...
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Figure 17: Copy Back Program Operation with Random Data Input Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 36 ...
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Figure 18: Block Erase Operation (Erase One Block) Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 37 ...
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Rev 0.4 / Jan. 2008 Figure 19: Multiple plane page program HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 38 ...
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Figure 20: Multiple plane erase operation Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 39 ...
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Figure 21: Multi plane copyback program Operation Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 1 40 ...
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Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 22: Read ID Operation HY27UF(08/16)4G2B Series 41 ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
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Figure 26: Power On and Data Protection Timing Rev 0.4 / Jan. 2008 Figure 25: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 43 ...
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Figure 27: Ready/Busy Pin electrical specifications Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 44 ...
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Figure 28: page programming within a block Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash 45 ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Bad Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 31~34) Rev 0.4 / Jan. 2008 4Gbit (512Mx8bit) NAND Flash Figure 31: ...
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Rev 0.4 / Jan. 2008 HY27UF(08/16)4G2B Series 4Gbit (512Mx8bit) NAND Flash Figure 33: Enable Erasing Figure 34: Disable Erasing 49 ...
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Figure 35. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 24: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev 0.4 / Jan. ...
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MARKING INFORMATION - ...