DS90CR215MTD National Semiconductor, DS90CR215MTD Datasheet - Page 14

• Manufacturer Part Number: DS90CR215MTD
• Description: Transmitter IC
• Manufacturer: National Semiconductor

Specifications of DS90CR215MTD

• Peak Reflow Compatible (260 C): No
• Supply Voltage: 3.3V
• Supply Voltage Max: 3.3V
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
RxCLK OUT
PWR DWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
Applications Information
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For
example, for lower data rate (clock rate) and shorter cable
lengths (
critical. For higher speed/long distance applications the me-
dia’s performance becomes more critical. Certain cable con-
structions provide tighter skew (matched electrical length
between the conductors and pairs). Twin-coax for example,
has been demonstrated at distances as great as 5 meters
and with the maximum data transfer of 1.38 Gbit/s. Addi-
tional applications information can be found in the following
National Interface Application Notes:
CABLES
A cable interface between the transmitter and receiver needs
to support the differential LVDS pairs. The 21-bit CHANNEL
LINK chipset (DS90CR215/216) requires four pairs of signal
wires and the 28-bit CHANNEL LINK chipset (DS90CR285/
286) requires five pairs of signal wires. The ideal cable/
connector interface would have a constant 100Ω differential
impedance throughout the path. It is also recommended that
cable skew remain below 150 ps (
maintain a sufficient data sampling window at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point
applications include flat ribbon, flex, twisted pair and Twin-
Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while Twin-
Coax is good for short and long applications. When using
ribbon cable, it is recommended to place a ground line
between each differential pair to act as a barrier to noise
coupling between adjacent pairs. For Twin-Coax cable ap-
plications, it is recommended to utilize a shield on each
cable pair. All extended point-to-point applications should
CC
AN-1041
AN-1035
AN-806
AN-905
AN-916
Pin Name
AN = ####
CC
CC
<
2m), the media electrical performance is less
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
Cable Information
I/O
O
1
I
I
I
I
I
I
DS90CR216 Pin Descriptions — Channel Link Receiver (Continued)
No.
1
1
4
5
1
2
1
3
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
@
Topic
66 MHz clock rate) to
(Continued)
14
also employ an overall shield surrounding all cable pairs
regardless of the cable type. This overall shield results in
improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver
and reduced problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI
reductions of LVDS, attention should be paid to the layout of
differential lines. Lines of a differential pair should always be
adjacent to eliminate noise interference from other signals
and take full advantage of the noise canceling of the differ-
ential signals. The board designer should also try to maintain
equal length on signal traces for a given differential pair. As
with any high speed design, the impedance discontinuities
should be limited (reduce the numbers of vias and no 90
degree angles on traces). Any discontinuities which do occur
on one signal line should be mirrored in the other line of the
differential pair. Care should be taken to ensure that the
differential trace impedance match the differential imped-
ance of the selected physical media (this impedance should
also match the value of the termination resistor that is con-
nected across the differential pair at the receiver’s input).
Finally, the location of the CHANNEL LINK TxOUT/RxIN pins
should be as close as possible to the board edge so as to
eliminate excessive pcb runs. All of these considerations will
limit reflections and crosstalk which adversely effect high
frequency performance and EMI.
UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must
be tied to ground. All unused outputs at the RxOUT outputs
of the receiver must then be left floating.
TERMINATION
Use of current mode drivers requires a terminating resistor
across the receiver inputs. The CHANNEL LINK chipset will
normally require a single 100Ω resistor between the true and
complement lines on each differential pair of the receiver
input. The actual value of the termination resistor should be
Description