DSPIC30F4011T-30I/ML Microchip Technology, DSPIC30F4011T-30I/ML Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F4011T-30I/ML
• Description: IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011T-30I/ML

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011T30IM

TABLE 2:
© 2010 Microchip Technology Inc.
Operations
Note 1:
OSC2 Pin
EEPROM
Module
Timer
PSV
Data
CAN
CAN
ADC
PLL
QEI
QEI
I/O
I
I
I
I
2
2
2
2
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Accumulation
Accumulation
Consumption
Bus Collision
RX Filters 3,
Timer Gated
Timer Gated
Using RC15
Sleep Mode
Lock Status
Error Count
Multiplexed
Addressing
Addressing
Addressing
for Digital
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Port Pin
with IC1
in Sleep
4 and 5
Current
10-bit
10-bit
10-bit
Mode
Mode
Mode
I/O
bit
—
—
Number
Item
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the
UART auto-baud feature is enabled.
When the I
using the same address bits (A10 and A9) as other I
devices, the A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from
Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally
get cleared and generate an oscillator failure trap even when
the PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
When the I
address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01 rather than 0x02.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a
bus collision in a multi-master configuration.
The Most Significant bit (MSb) of every fourth byte in Data
EEPROM may be corrupted
If the pin RC15 is required for digital input/output, the
FPR<4:0> bits in the FOSC Configuration register may not
be set up for FRC w/PLL 4x/8x/16x modes.
CAN Receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time
quanta.
The C1EC register does not reflect the correct error count
value.
When Timer Gated Accumulation is enabled, the QEI does
not generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an
external signal is applied, the POSCNT increments and
generates an interrupt after a match with MAXCNT.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
2
2
2
C module is configured for 10-bit addressing
C module is configured as a 10-bit slave with an
C module is enabled, the dsPIC
Issue Summary
.
dsPIC30F4011/4012
®
DSC device
PD
) of the
2
C
A1 A2 A3 A4
DS80454D-page 3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X