DSPIC30F4011T-30I/ML Microchip Technology, DSPIC30F4011T-30I/ML Datasheet - Page 4

• Manufacturer Part Number: DSPIC30F4011T-30I/ML
• Description: IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011T-30I/ML

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011T30IM

dsPIC30F4011/4012
Silicon Errata Issues
1. Module: CPU
DS80454D-page 4
Note:
Sequential MAC class instructions, which prefetch
data from Y data space using ±4 address
modification, will cause an address error trap. The
trap occurs only when all of the following
conditions are true:
1. Two sequential MAC class instructions (or a
2. Both instructions prefetch data from Y data
3. Neither of the instruction uses an accumulator
Work around
The problem described above can be avoided by
using any of the following methods:
1. Inserting any other instruction between the two
2. Adding an accumulator write back (a dummy
3. Do not use the + = 4 or - = 4 address
4. Do not prefetch data from Y data space.
Affected Silicon Revisions
A1
X
MAC class instruction executed in a REPEAT or
DO loop) that prefetch from Y data space.
space using the + = 4 or - = 4 address
modification.
write back.
MAC class instructions.
write back if needed) to either of the MAC class
instructions.
modification.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A2
X
A3
X
A4
X
2. Module: CPU
EXAMPLE 1:
3. Module: I/O
L0:DAW.b
L1: ....
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. Example 1 shows how the application
should process the Carry bit during a BCD addition
operation.
Affected Silicon Revisions
The I/O Port register values can be changed by
writing to the following address locations, which
are located in unimplemented memory space. A
write to these unimplemented addresses could
cause an I/O pin configured as an output to
change states. This state change could be
confirmed by reading either the PORT or LAT
register associated with the pin.
PORTB will be modified by a write to address 0x0C8
PORTC will be modified by a write to address 0x0CE
PORTD will be modified by a write to address 0x0D4
PORTE will be modified by a write to address 0x0DA
PORTF will be modified by a write to address 0x0E0
Work around
User software should avoid writing to the
unimplemented locations listed above.
Affected Silicon Revisions
.include “p30fxxxx.inc”
.......
MOV.b
MOV.b
ADD.b
BRA
DAW.b
BSET.b
BRA
A1
A1
X
X
A2
A2
X
X
#0x80, w0
#0x80, w1
w0, w1, w2 ;Perform addition
NC, L0
w2
L1
w2
SR, #C
A3
A3
X
X
CHECK CARRY BIT BEFORE
DAW.b
© 2010 Microchip Technology Inc.
A4
A4
X
X
;First BCD number
;Second BCD number
;If C set go to L0
;If not,do DAW and
;set the carry bit
;and exit