HCTL-2021-A00 Avago Technologies US Inc., HCTL-2021-A00 Datasheet - Page 5

• Manufacturer Part Number: HCTL-2021-A00
• Description: IC,Servo Encoder,CMOS,DIP,20PIN,PLASTIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2021-A00

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 20-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1883-5; HCTL-2021-A00

Table 4b. Functional Pin Descriptions (PLCC Package)
5
CLK
CHA
CHB
RST
OE
CNTDCDR NA
U/D
CNTCAS
D0
D1
D2
D3
D4
D5
D6
D7
Symbol
VDD
VSS
SEL
Pin
HCTL
2017-PLC
20
10
2
9
8
7
NA
NA
1
19
18
17
14
13
12
11
4
3
HCTL
2021-PLC
20
10
2
9
8
7
4
3
16
5
15
1
19
18
17
14
13
12
11
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
position latch. It also resets the inhibit logic. RST is asynchronous with respect
inputs are sampled by the internal inhibit logic on the falling edge of the clock to
internal counter overflows or underflows. The rising edge on this waveform may
be used to trigger an external counter.
High byte is read first followed by the Low bytes.
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and the
to any other input signals.
This CMOS active low input enables the tri-state output buffers. The OE/ and SEL
control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control
the internal inhibit logic.
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDCDR and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before
the rising edge of the CNTDCDR and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-PLC
These LSTTL-compatible tri-state outputs form an 8-bit output ports through which
the contents of the 16-bit position latch may be read in 2 sequential bytes. The
SEL
0
1
BYTE SELECTED
High
Low