HCTL-2021-A00 Avago Technologies US Inc., HCTL-2021-A00 Datasheet - Page 8

• Manufacturer Part Number: HCTL-2021-A00
• Description: IC,Servo Encoder,CMOS,DIP,20PIN,PLASTIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2021-A00

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 20-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1883-5; HCTL-2021-A00

Figure 6. Simplified Logic Diagram
Digital Noise Filter
The digital noise filter section is responsible for
rejecting noise on the incoming quadrature signals. The
input section uses two techniques to implement
improved noise rejection. Schmitt-trigger inputs and a
three-clock-cycle delay filter combine to reject low level
noise and large, short duration noise spikes that
typically occur in motor system applications. Both
common mode and differential mode noise are
rejected. The user benefits from these techniques by
improved integrity of the data in the counter. False
counts triggered by noise are avoided.
Figure 7 shows the simplified schematic of the input
section. The signals are first passed through a Schmitt-
trigger buffer to address the problem of input signals
8
with slow rise times and low-level noise (approximately
< 1V). The cleaned up signals are then passed to a
four-bit delay filter. The signals on each channel are
sampled on rising clock edges. A time history of the
signals is stored in the four-bit shift register. Any
change on the input is tested for a stable level being
present for three consecutive rising clock edges.
Therefore, the filtered output waveforms can change
only after an input level has the same value for three
consecutive rising clock edges.
Refer to Figure 8, which shows the timing diagram.
The result of this circuitry is that short noise spikes
between rising clock edges are ignored and pulses
shorter than two clock periods are rejected.