LM2641MTC-ADJ National Semiconductor, LM2641MTC-ADJ Datasheet - Page 13

• Manufacturer Part Number: LM2641MTC-ADJ
• Description: Power Supply IC
• Manufacturer: National Semiconductor

Specifications of LM2641MTC-ADJ

• Power Dissipation Pd: 883mW
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
The components shown will add poles and zeros to the loop
gain as given by the following equations:
C10 adds a pole whose frequency is given by:
C12 adds a pole whose frequency is given by:
R11 adds a zero whose frequency is given by:
The output capacitor adds both a pole and a zero to the loop:
Where R
series resistance of the output capacitor(s).
The function of the compensation components will be ex-
plained in a qualitative discussion of a typical loop gain plot
for an LM2641 application, as illustrated in Figure 5 .
C10 and R11 form a pole and a zero. Changing the value of
C10 moves the frequency of both the pole and the zero.
Changing R11 moves the zero without significantly affecting
the pole.
The C10 pole is typically referred to as the dominant pole,
and its primary function is to roll off loop gain and reduce the
bandwidth.
The R11 zero is required to add some positive phase shift to
offset some of the negative phase shift from the two
low-frequency poles. Without this zero, these two poles
would cause −180˚ of phase shift at the unity-gain crossover,
which is clearly unstable. Best results are typically obtained
f
f
f
f
f
p
p
z
p
z
(C10) = 1 / [2 X C10 (R11 + 160k) ]
(C12) = 1 / [2 X C12 (R11 || 160k) ]
(R11) = 1 / [2 X R11 (C10 + C12) ]
(C
(ESR) = 1 / [2 X ESR X C
OUT
FIGURE 4. Typical Compensation Network
L
) = 1 / [2 X R
is the load resistance, and ESR is the equivalent
FIGURE 5. Typical Loop Gain Plot
L
X C
OUT
OUT
]
]
(Continued)
DS100949-6
DS100949-5
13
if R11 is selected such that the frequency of f
range of f
quency.
The output capacitor (along with the load resistance R
forms a pole shown as f
this pole varies with R
ally which means the unity-gain crossover frequency stays
essentially constant regardless of R
C12 can be used to create an additional pole most often
used for bypassing high-frequency switching noise on the
COMP pin. In many applications, this capacitor is unneces-
sary.
If C12 is used, best results are obtained if the frequency of
the pole is set in the range F
bypassing for the high-frequency noise caused by switching
transitions, but add only a small amount of negative phase
shift at the unity-gain crossover frequency.
The ESR of C
the zero f
10kHz and 50kHz. This zero is very important, as it cancels
phase shift caused by the high-frequency pole f
important to select C
tance and ESR to place this zero near f
f
As an example, we will present an analysis of the loop gain
plot for a 3.3V design. Values used for calculations are:
The values of compensation components will be: C10 =
2200 pF, R11 = 8.2k, and C12 will not be used. Using this
data, the poles and zeros are calculated:
Using these values, the calculated gain plot is shown in Fig-
ure 6 .
c
).
V
V
C
ESR = 60 m (each) = 30m
F
f
R13 = 20m
L2 = 6.8 µH
R
DC gain = 55dB
f
f
f
f
f
p
p
z
p
z
p
OSC
IN
OUT
(R11) = 1 / [2 X R11 (C10 + C12) ] = 8.8kHz
(ESR) = 1 / [2 X ESR X C
OUT
(HF)
L
(C10) = 1 / [2 X C10 (R11 + 160k) ] = 430Hz
(C
(HF)
= 0.825
OUT
= 12V
= 3.3V
= 300kHz
= C14 + C16 = 200 µF
z
) = 1 / [2 X R
c
(ESR), which typically falls somewhere between
/4 to f
40kHz
40kHz
OUT
@
c
(as well as the capacitance of C
4A
where f
OUT
L
, the loop gain also varies proportion-
p
L
(C
with the correct value of capaci-
X C
c
OSC
OUT
is the unity-gain crossover fre-
OUT
). Although the frequency of
/2 to 2F
OUT
total
] = 960Hz
] = 27kHz
L
value.
c
OSC
(typical range f
. This will provide
z
(R11) is in the
www.national.com
p
(HF). It is
OUT
) form
c
/2 to
L
)