PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 109

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

12.5
The PIC16C925/926 family has nine sources of
interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts
• A/D Interrupt
• TMR1 overflow interrupt
• TMR2 matches period interrupt
• CCP1 interrupt
• Synchronous serial port interrupt
• LCD module interrupt
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
FIGURE 12-10:
(pins RB7:RB4)
Note:
2001 Microchip Technology Inc.
Interrupts
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
ADIF
ADIE
TMR1IF
TMR1IE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
INTERRUPT LOGIC
LCDIF
LCDIE
Preliminary
TMR0IF
TMR0IE
GIE
INTF
INTE
RBIF
RBIE
PEIF
PEIE
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function register, PIR1. The corresponding inter-
rupt enable bits are contained in special function
register, PIE1, and the peripheral interrupt enable bit is
contained in special function register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin
or RB Port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends
(Figure 12-11). The latency is the same for one or two
cycle instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask
bit, PEIE bit, or the GIE bit.
when
PIC16C925/926
the
interrupt
Wake-up (If in SLEEP mode)
DS39544A-page 107
Interrupt to CPU
event
occurs