PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 74

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

PIC16C925/926
9.3.2
Master mode of operation is supported, in firmware,
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET, or when the
SSP module is disabled. The STOP and START bits
will toggle based on the START and STOP conditions.
Control of the I
set, or the bus is idle with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 9-4:
DS39544A-page 72
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
13h
93h
14h
94h
87h
Legend:
Address
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by SSP in I
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
MASTER MODE
Name
2
C bus may be taken when the P bit is
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
WCOL
LCDIF
LCDIE
Bit 7
SMP
GIE
—
SSPOV SSPEN
Bit 6
PEIE
ADIF
ADIE
CKE
—
PORTC Data Direction Control Register
TMR0IE
Bit 5
D/A
—
—
2
C mode) Address Register
Preliminary
Bit 4
INTE
CKP
—
—
P
SSPM3 SSPM2 SSPM1 SSPM0
2
SSPIE CCP1IE TMR2IE TMR1IE
SSPIF
RBIE
C OPERATION
Bit 3
S
9.3.3
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP and
START bits will toggle based on the START and STOP
conditions. Control of the I
bit P (SSPSTAT<4>) is set, or the bus is idle, with both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, they are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
TMR0IF
CCP1IF TMR2IF TMR1IF
Bit 2
R/W
MULTI-MASTER MODE
Bit 1
INTF
UA
Bit 0
RBIF
BF
2001 Microchip Technology Inc.
2
C bus may be taken when
0000 000x
00-- 0000
00-- 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
--11 1111
Power-on
Value on
Reset
2
C mode.
Value on all
0000 000u
00-- 0000
00-- 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
--11 1111
RESETS
other