PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 110

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

PIC16C925/926
FIGURE 12-11:
12.5.1
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.8 for details on SLEEP mode.
DS39544A-page 108
INT pin
INTF Flag
(INTCON<1>)
INSTRUCTION FLOW
OSC1
CLKOUT
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 T
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF can be set any time during the Q4-Q1 cycles.
on
INT INTERRUPT
3
cycle or a 2-cycle instruction.
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
INT PIN INTERRUPT TIMING
1
Q2
PC
Q3
4
pin,
Q4
5
CY
where T
Q1
flag
Inst (PC+1)
Inst (PC)
Q2
1
bit
CY
PC+1
= instruction cycle time. Latency is the same whether Inst (PC) is a single
Q3
INTF
Preliminary
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
12.5.2
An overflow (FFh
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>) (Section 5.0).
12.5.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<4>)
(Section 4.2).
PC+1
—
Q3
Q4
2
TMR0 INTERRUPT
PORTB INTCON CHANGE
Q1
Dummy Cycle
Inst (0004h)
Q2
by
0004h
00h) in the TMR0 register will set
Q3
setting/clearing
2001 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
enable
Q3
Q4
bit,