PIC16C926-I/PT Microchip Technology, PIC16C926-I/PT Datasheet - Page 120

• Manufacturer Part Number: PIC16C926-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C926-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C926I/PT

PIC16C925/926
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
DS39544A-page 118
Before Instruction:
After Instruction:
If Skip:
PC
if FLAG<1> =
PC
if FLAG<1> =
PC
Bit Test f, Skip if Set
[ label ] BTFSS f [,b]
0
0
skip if (f<b>) = 1
None
If bit ’b’ in register ’f’ is ’0’, then the
next instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOP is exe-
cuted instead, making this a 2T
instruction.
1
1(2)
HERE
FALSE
TRUE
(2nd Cycle)
Operation
Decode
Q1
Q1
=
=
=
01
No
f
b < 7
127
address HERE
0,
address FALSE
1,
address TRUE
BTFSC
GOTO
•
•
•
register ’f’
Operation
11bb
Read
Q2
Q2
No
FLAG,1
PROCESS_CODE
Operation
Process
bfff
data
Q3
Q3
No
Operation
Operation
ffff
Q4
Q4
No
No
CY
Preliminary
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Before Instruction:
After Instruction:
2nd Cycle
1st Cycle
PC
PC
TOS
= Address HERE
= Address THERE
= Address HERE+1
Call Subroutine
[ label ] CALL k
0
(PC)+ 1
k
(PCLATH<4:3>)
None
Call Subroutine. First, return
address (PC+1) is pushed onto the
stack. The eleven-bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC are
loaded from PCLATH. CALL is a
two-cycle instruction.
1
2
HERE
Operation
Decode
Q1
10
No
k
PC<10:0>,
2001 Microchip Technology Inc.
2047
CALL
Operation
Push PC
literal ’k’,
to Stack
TOS,
0kkk
Read
Q2
No
Operation
Process
THERE
PC<12:11>
kkkk
data
Q3
No
Operation
Write to
kkkk
Q4
PC
No