AS5163-HTST-500 austriamicrosystems, AS5163-HTST-500 Datasheet - Page 17

• Manufacturer Part Number: AS5163-HTST-500
• Description: IC ENCODER ROTARY 14-TSSOP
• Manufacturer: austriamicrosystems
• Type: Linear, Rotary Encoder - Programmabler

Specifications of AS5163-HTST-500

• Featured Product: AS5163 - Contactless Magnetic Angle Position Sensor
• Sensing Range: 30mT ~ 70mT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Output Type: Analog, Ratiometric
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output (max): -
• Features: -
• Other names: AS5163-HTST-500TR

AS5163
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.2 Protocol Timing and Commands of Single Pin Interface
During the communication mode, the output level is defined by the external pull up resistor R
state. The bit coding
required due to the tolerance of the internal clock frequency.
the clock T
The voltage levels V
Each frame is composed by 20 bits. The 4 MSB (CMD) of the frame specifies the type of command that is passed to the AS5163. The 16 data
bits contain the communication data. There will be no operation when the ‘not specified’ CMD is used. The sequence is oriented in such a way
that the LSB of the data is followed by the command. The number of frames vary depending on the command. The single pin programming
interface block of the AS5163 can operate in slave communication or master communication mode. In the slave communication mode, the
AS5163 receives the data organized in frames. The programming tool is the driver of the single communication line and can pull down the level.
In case of the master communication mode, the AS5163 transmits data in the frame format. The single communication line can be pulled down
by the AS5163.
Figure 12. Bit Coding of the Single Pin Programming Interface
Figure 13. Protocol Definition
www.austriamicrosystems.com/AS5163
CLK
is defined with 222.2 ns.
H
(see Figure 18)
and V
IDLE START
L
V
V
are CMOS typical.
H
L
has been chosen in order to allow the continuous synchronization during the communication, which can be
T
T
1
2
= 128 * T
= 384 * T
T
1
Bit “0”
CLK
CLK
T
2
Figure 18
DATA
PACKET
Revision 2.7
shows how the different logic states '0' and '1' are defined. The period of
V
V
H
L
T
BIT
= T
1
Communication
+ T
T
1
2
= 512 * T
Bit “1”
COMMAND
CLK
. The output driver of the device is in tri-
T
2
IDLE
START
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