TLE4998C3 Infineon Technologies, TLE4998C3 Datasheet - Page 28

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TLE4998C3

Manufacturer Part Number
TLE4998C3
Description
IC HALL SENSOR LINEAR SSO-3
Manufacturer
Infineon Technologies
Type
Linear - Programmabler
Datasheet

Specifications of TLE4998C3

Sensing Range
-200mt Trip ~ 200mT Release
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Current - Output (max)
5mA
Output Type
Digital, PWM (Current)
Operating Temperature
-40°C ~ 150°C
Package / Case
3-SSO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
SP000476468
9.1
When the MEMLOCK bits are programmed (two redundant bits), the memory content is
frozen and may no longer be changed. Furthermore, the programming interface is locked
out and the chip remains in application mode only, preventing accidental programming
due to environmental influences.
Figure 8
A matrix parity architecture allows automatic correction of any single-bit error. Each row
is protected by a row parity bit. The sum of bits set (including this bit) must be an odd
number (ODD PARITY). Each column is additionally protected by a column parity bit.
Each bit in the even positions (0, 2, etc.) of all lines must sum up to an even number
(EVEN PARITY), and each bit in the odd positions (1, 3, etc.) must have an odd sum
(ODD PARITY). The parity column must have an even sum (EVEN PARITY).
This system of different parity calculations also protects against many block errors (such
as erasing a full line or even the whole EEPROM).
When modifying the application bits (such as Gain, Offset, TC, etc.), the parity bits must
be updated. As for the column bits, the pre-calibration area must be read out and
considered for correct parity generation as well.
Note: A specific programming algorithm must be followed to ensure data retention.
Data Sheet
A detailed separate programming specification is available on request.
Calibration Data Memory
EEPROM Map
User-Calibration Bits
Pre-Calibration Bits
Column Parity Bits
28
TLE4998C3C
Rev 1.1, 2009-09
Calibration

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