CV500RT221 Omron, CV500RT221 Datasheet - Page 160

• Manufacturer Part Number: CV500RT221
• Description: Programmable Logic Controller
• Manufacturer: Omron

Specifications of CV500RT221

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Alphabetic List of Instructions by Mnemonics
Note Instructions with one asterisk (*) are supported by the CVM1D and version-2 CVM1 CPU Units only.
RAD(j)*
RD2*
READ
RECV(j)
REGL(j)
REGS(j)
RET
RLNC(j)*
RLNL(j)*
ROL(j)
ROLL(j)
ROOT(j)
ROR(j)
RORL(j)
ROTB(j)*
RRNC(j)*
RRNL(j)*
RSET(!ji)
RSTA(j)*
SA(j)**
SBB(j)
SBBL(j)
SBN
SBS(j)
SDEC(j)
SE(j)**
SEC(j)
SEND(j)
SET(!ji)
SETA(j)*
SF(j)**
SFT
SFTR(j)
SIGN(j)
SIN(j)*
SLD(j)
SNXT
SOFF(j)**
SP(j)**
Mnemonic
Instructions with two asterisks (**) are supported by the CV500, CV1000, and CV2000 only.
Instructions with three asterisks (***) are not supported by the CVM1D.
458
280
190
193
175
176
152
260
262
062
066
140
063
067
274
261
263
017
048
210
081
085
150
151
112
214
143
192
016
047
213
050
051
106
460
068
009
215
211
Code
DEGREES-TO-RADIANS
I/O READ 2
I/O READ
NETWORK RECEIVE
LOAD REGISTER
SAVE REGISTER
SUBROUTINE RETURN
ROTATE LEFT WITHOUT
CARRY
DOUBLE ROTATE LEFT
WITHOUT CARRY
ROTATE LEFT WITH CARRY
DOUBLE ROTATE LEFT WITH
CARRY
BCD SQUARE ROOT
ROTATE RIGHT WITH CARRY
DOUBLE ROTATE RIGHT
WITH CARRY
BINARY ROOT
ROTATE RIGHT WITHOUT
CARRY
ROTATE LEFT WITHOUT
CARRY
RSET
MULTIPLE BIT RESET
ACTIVATE STEP
BINARY SUBTRACT
DOUBLE BINARY SUBTRACT
SUBROUTINE ENTER
SUBROUTINE CALL
7-SEGMENT DECODER
DEACTIVATE STEP
HOURS-TO-SECONDS
NETWORK SEND
SET
MULTIPLE BIT SET
END STEP
SHIFT REGISTER
REVERSIBLE SHIFT
REGISTER
SIGN
SINE
SHIFT DIGIT LEFT
STEP START
RESET STEP
PAUSE STEP
Name
SQRT(j)*
SR(j)**
SRCH(j)
SRD(j)
SSET(j)
STC(j)
STEP
SUB(j)
SUBL(j)
SUM(j)
TAN(j)*
TCMP(j)
TCNT**
TIMH
TIML
TIMW*
TMHW*
TOUT**
TRSM
TSR(j)**
TST*
TSTN*
TSW(j)**
TTIM
UP*
WAIT(NOT)
*
WDT*
WR2*
WRIT
WSFT(j)
XCGL(j)
XCHG(j)
XFER(j)
XFRB(j)*
XNRL(j)
XNRW(j)
XORL(j)
XORW(j)
ZONE(j)*
/(j)*
/B(j)*
/BL(j)*
Mnemonic
466
212
164
069
160
078
008
071
075
167
462
023
123
015
121
<013>
<015>
202
170
124
350
351
125
120
018
<005>
178
281
191
053
035
034
040
038
137
133
136
132
273
430
434
435
Code
SQUARE ROOT
RESTART STEP
DATA SEARCH
SHIFT DIGIT RIGHT
SET STACK
SET CARRY
STEP DEFINE
BCD SUBTRACT
DOUBLE BCD SUBTRACT
SUM
TANGENT
TABLE COMPARE
TRANSITION COUNTER
HIGH-SPEED TIMER
DOUBLE TIMER
TIMER WAIT
HIGH-SPEED TIMER WAIT
TRANSITION OUTPUT
TRACE MEMORY
READ STEP TIMER
BIT TEST
BIT TEST
WRITE STEP TIMER
ACCUMULATIVE TIMER
CONDITION ON
1-SCAN WAIT
MAXIMUM CYCLE TIME
EXTEND
I/O UNIT WRITE 2
I/O WRITE
WORD SHIFT
DOUBLE DATA EXCHANGE
DATA EXCHANGE
BLOCK TRANSFER
MULTIPLE BIT TRANSFER
DOUBLE EXCLUSIVE NOR
EXCLUSIVE NOR
DOUBLE EXCLUSIVE OR
EXCLUSIVE OR
DEAD-ZONE CONTROL
SIGNED BINARY DIVIDE
BCD DIVIDE
DOUBLE BCD DIVIDE
Name
Appendix F
155