ADNS-3530 Avago Technologies US Inc., ADNS-3530 Datasheet - Page 9

• Manufacturer Part Number: ADNS-3530
• Description: Small Form Factor COB LED Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-3530

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25°C, V
9
Parameter
Motion Delay After Reset
Shutdown
Wake from Shutdown
Forced Rest Enable
Wake from Forced Rest
MISO Rise Time
MISO Fall Time
MISO Delay After SCLK
MISO Hold Time
MOSI Hold Time
MOSI Setup Time
SPI Time Between Write Com-
mands
SPI Time Between Write and
Read Commands
SPI Time Between Read and
Subsequent Commands
SPI Read Address-Data
Delay
NCS Inactive After Motion
Burst
NCS to SCLK Active
SCLK to NCS Inactive
(for Read Operation)
SCLK to NCS Inactive
(for Write Operation)
NCS to MISO High-Z
MOTION Rise Time
MOTION Fall Time
SHTDWN Pulse Width
Transient Supply Current
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I
DDT
MOT-RST
SHTDWN
WAKEUP
REST-EN
REST-DIS
r-MISO
f-MISO
DLY-MISO
hold-MISO
hold-MOSI
setup-MOSI
SWW
SWR
SRW
SRR
SRAD
BEXIT
NCS-SCLK
SCLK-NCS
SCLK-NCS
NCS-MISO
r-MOTION
f-MOTION
P-SHTDWN
Min.
1
0.5
30
20
500
4
500
120
120
20
1
200
120
Typical
150
150
150
150
Max.
23
50
1
1
300
300
120
1/f
500
300
300
45
SCLK
Units
ms
ms
s
s
s
ns
ns
ns
μs
ns
ns
μs
μs
ns
μs
ns
ns
ns
us
ns
ns
ns
s
mA
Notes
From POWER_UP_RESET register write to
valid motion, assuming motion is present
From SHTDWN pin active to low current
From SHTDWN pin inactive to valid mo-
tion. Notes: A RESET must be asserted
after a shutdown. Refer to section “Notes
on Shutdown and Forced Rest, ” also note
t
From RESTEN bits set to low current
From RESTEN bits cleared to valid motion
C
C
From SCLK falling edge to MISO data
valid, no load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK
rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first
data byte, to rising SCLK for last bit of the
second data byte
From rising SCLK for last bit of the first
data byte, to rising SCLK for last bit of the
second address byte
From rising SCLK for last bit of the first
data byte, to falling SCLK for the first bit of
the address byte of the next command
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read
Minimum NCS inactive time after motion
burst before next SPI usage
From NCS falling edge to first SCLK rising
edge
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising
edge, for valid MOSI data transfer
From NCS rising edge to MISO high-Z
state
C
C
Max supply current during a V
from 0 to 2.8 V
MOT-RST
L
L
L
L
= 100 pF
= 100 pF
= 100 pF
= 100 pF
DD3
= 2.85 V.
DD
ramp