XR21V1412IL-0B-EB Exar Corporation, XR21V1412IL-0B-EB Datasheet
XR21V1412IL-0B-EB
Specifications of XR21V1412IL-0B-EB
Related parts for XR21V1412IL-0B-EB
XR21V1412IL-0B-EB Summary of contents
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SEPTEMBER 2010 GENERAL DESCRIPTION The XR21V1412 (V1412 enhanced 2-channel Universal Asynchronous Receiver and Transmitter (UART) with a USB interface. The USB interface is fully compliant to Full Speed USB 2.0 specification that supports 12 Mbps USB data transfer ...
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XR21V1412 2-CH FULL-SPEED USB UART F 1. XR21V1412 B D IGURE LOCK IAGRAM 3.3V VCC GND USB Slave USBD+ Interface USBD SDA Interface SCL Internal 48MHz Oscillator 128-byte TX FIFO Fractional BRG 384-byte RX FIFO Internal Status ...
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... REV. 1.1 IGURE IN UT SSIGNMENT SDA 25 SCL 26 GND 27 GND 28 USBD USBD+ 31 VCC VCC 32 ORDERING INFORMATION P N ART UMBER XR21V1412IL32 32-pin QFN 32-pin QFN GPIOA2/DSRA# 9 GPIOA3/DTRA ACKAGE PERATING EMPERATURE -40° +85° XR21V1412 2-CH FULL-SPEED USB UART RXB TXB GND VCC GPIOA0/RIA# GPIOA1/CDA# ...
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XR21V1412 2-CH FULL-SPEED USB UART PIN DESCRIPTIONS Pin Description 32-QFN N T AME YPE UART Channel A Signals RXA 6 I UART Channel A Receive Data or IR Receive Data. This pin has an internal pull-up resistor. ...
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REV. 1.1.0 Pin Description 32-QFN N T AME YPE I/O GPIOB1/CDB# UART Channel B general purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. ...
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XR21V1412 2-CH FULL-SPEED USB UART Pin Description 32-QFN N T AME YPE Miscellaneous Signals 2 O LOWPOWER Low power status output. This pin will be asserted whenever the V1412 device is placed into the suspend state. This ...
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REV. 1.1.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 USB interface The USB interface of the V1412 is compliant with the USB 2.0 Full-Speed Specifications. The USB configuration model presented by the V1412 to the device driver is compatible to the Abstract Control ...
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XR21V1412 2-CH FULL-SPEED USB UART 2 1 Interface 2 The I C interface provides connectivity to an external I the V1412 for configuration. The SDA and SCL are used to specify whether Remote Wakeup and/or Bus Powered configurations ...
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REV. 1.1.0 Bit 6 is Self-powered mode - set to ’0’ for bus-powered, set to ’1’ for self-powered Bit 5 is Remote Wakeup support - set to ’0’ for no support, set to ’1’ for remote wakeup support Bit 4:0 ...
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XR21V1412 2-CH FULL-SPEED USB UART bit m ode 1st byte 2nd byte 1st byte ...
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REV. 1.1 RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts ...
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XR21V1412 2-CH FULL-SPEED USB UART 1.5.7.1 Receiver If an address match occurs in either flow control mode the address byte will not be loaded into the RX FIFO, but all subsequent data bytes will be loaded into ...
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REV. 1.1.0 2.0 USB CONTROL COMMANDS The following table shows all of the USB Control Commands that are supported by the V1412. Commands included are standard USB commands, CDC-ACM commands and custom Exar commands ABLE R EQUEST N ...
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XR21V1412 2-CH FULL-SPEED USB UART T ABLE R EQUEST N AME T YPE CDC_ACM_IF 0x21 SEND_BREAK XR_SET_REG 0x40 XR_GETN_REG 0xC0 2.1 UART Block Numbers The table below lists the block numbers for accessing each of the UART channels and the ...
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REV. 1.1.0 3.0 REGISTER SET DESCRIPTION The internal register set of the V1412 consists of 3 different blocks of registers: the UART Manager, UART registers and UART miscellaneous registers. The UART Manager controls the TX and RX enables and FIFOs ...
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XR21V1412 2-CH FULL-SPEED USB UART 3.2 UART Register Map DDRESS EGISTER AME 0X00 Reserved 0X01 Reserved 0X02 Reserved 0X03 UART_ENABLE 0X04 CLOCK_DIVISOR0 0x05 CLOCK_DIVISOR1 0x06 CLOCK_DIVISOR2 0x07 TX_CLOCK_MASK0 0x08 TX_CLOCK_MASK1 0x09 RX_CLOCK_MASK0 0x0A RX_CLOCK_MASK1 0x0B CHARACTER_FORMAT 0x0C ...
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REV. 1.1.0 3.3 UART Register Descriptions 3.3.1 UART_ENABLE Register Description (Read/Write) This register enables the UART TX and RX. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 ...
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XR21V1412 2-CH FULL-SPEED USB UART ABLE LOCK IVISOR AND AUD ATE BPS LOCK 1200 2400 4800 9600 19200 38400 57600 115200 230400 460800 500000 576000 921600 1000000 1152000 1500000 2000000 2500000 ...
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REV. 1.1 NDEX ECIMAL ...
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XR21V1412 2-CH FULL-SPEED USB UART 3.3.5 CHARACTER_FORMAT Register Description (Read/Write) This register controls the character format such as the word length ( 9), parity (odd, even, forced ’0’, or forced ’1’) and number of stop bits (1 or ...
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REV. 1.1.0 FLOW_CONTROL[2:0]: Flow control mode select T ABLE ODE ...
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XR21V1412 2-CH FULL-SPEED USB UART ERROR_STATUS[4]: Framing Error Logic framing error Logic framing error has been detected (clears after read). A framing error occurs when a stop bit is not present when it is ...
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REV. 1.1.0 3.3.11 GPIO_MODE Register Description (Read/Write) GPIO_MODE[2:0]: GPIO Mode Select There are 4 modes of operation for the GPIOs. The descriptions can be found in page 9. BITS GPIO0 GPIO1 GPIO2 [2:0] 000 GPIO0 GPIO1 GPIO2 001 GPIO0 GPIO1 ...
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XR21V1412 2-CH FULL-SPEED USB UART 3.3.14 GPIO_SET Register Description (Read/Write) Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ bit has no effect. Bits 7-6 are unused and should be ’0’. 3.3.15 GPIO_CLEAR ...
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REV. 1.1.0 3.4.2 LOW_LATENCY Register Description (Read/Write) This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud rates of 46921 bps and higher. This register enables the Low latency ...
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XR21V1412 2-CH FULL-SPEED USB UART S IZE O F FFSET IELD (B YTES 0 bmRequestType 1 1 bNotification 1 2 wValue 2 4 wIndex 2 6 wLength 2 8 Data 2 T 17: D ABLE ...
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REV. 1.1 ABLE ATA IELD IELD 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 ...
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XR21V1412 2-CH FULL-SPEED USB UART 4.0 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS - POWER CONSUMPTION -40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER I Power Supply Current CC I Suspend mode Current Susp DC ELECTRICAL CHARACTERISTICS - ...
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REV. 1.1.0 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 ...
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... Clarified pin functionality, wide mode and low latency mode including registers / blocks, clarified FLOW_CONTROL and GPIO_MODE register functionality. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...