LFE3-95EA-PCIE-DKN Lattice, LFE3-95EA-PCIE-DKN Datasheet - Page 19

• Manufacturer Part Number: LFE3-95EA-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3-95EA PCI Express Dev Kit
• Manufacturer: Lattice
• Series: ECP3r

Specifications of LFE3-95EA-PCIE-DKN

• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeECP3
• Kit Contents: Board
• Features: On-board Boot Flash, Switches, LEDs, Displays For Demo Purposes
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Main Purpose: Interface, Connectivity
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: LatticeECP3 FPGA Device Family
• Primary Attributes: x1/x4 PCI Express Edge Connectors, Both Serial SPI Flash and Parallel Flash
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
General-Purpose Header
(see Appendix A, Figure 27, J5)
A 2x9 header (J5) provides a general-purpose connection to communicate with general purpose FPGA I/Os.
Table 13. General Purpose Header Connections
17-Segment LED Display
(see Appendix A, Figure 27, D13)
General-purpose FPGA pins are connected to a 17-segment display according to Table 14. These pins can be
driven low to illuminate the display segments.
Table 14. 17-Segment LED Display
Logic Analyzer Probe
(see Appendix A, Figure 27, LA1)
An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to uti-
lize for test points. This connection provides 34 general I/O signals to be observed on a Logic Analyzer probe using
Mictor connections such as the Agilent 5346A.
Header Pin
11
13
15
17
1
3
5
7
9
Segment
DP
G
M
A
B
C
D
E
H
K
N
P
R
S
U
F
T
FPGA Pin
LatticeECP3 PCI Express Solutions Board – Revision A
GND
C15
B15
C14
D14
B16
C16
F13
F14
BGA
H8
G7
C8
D8
C5
C6
D6
C4
D5
C7
B7
F8
F7
A4
A3
B4
B6
19
G
Header Pin
H
F
10
12
14
16
18
2
4
6
8
T S
U
K M N
A
E
R
P
B
D
C
DP
FPGA Pin
GND
E15
E14
A20
A19
C17
B17
A18
A17
User’s Guide