UPD43256BGU-85L

Manufacturer Part NumberUPD43256BGU-85L
DescriptionIC'S
ManufacturerNEC
UPD43256BGU-85L datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Page 1/24

Download datasheet (175Kb)Embed
Next
Description
The PD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations.
The PD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Wide voltage range (A version: V
• 2 V data retention
• OE input for easy application
Access time
Part number
ns (MAX.)
PD43256B-L
70, 85
PD43256B-LL
70, 85
Note 2
PD43256B-A
85, 100
, 120
Note 2
PD43256B-B
100, 120, 150
Notes 1. T
40 ˚C, V
A
CC
2. Access time : 85 ns (MAX.) (V
Version X and P
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in
the fifth character position in a lot number signifies version X, letter P, version P.
The information in this document is subject to change without notice.
Document No. M10770EJ9V0DS00 (9th edition)
Date Published May 1997 N
Printed in Japan
DATA SHEET
MOS INTEGRATED CIRCUIT
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
= 3.0 to 5.5 V, B version: V
CC
CC
Operating
Operating
supply voltage
temperature
V
C
4.5 to 5.5
0 to 70
Note 2
3.0 to 5.5
2.7 to 5.5
= 3 V
= 4.5 to 5.5 V)
CC
JAPAN
D43256B
Lot number
The mark
shows major revised points.
PD43256B
= 2.7 to 5.5 V)
Standby
Data retention
Note 1
supply current
supply current
A (MAX.)
A (MAX.)
50
3
15
2
©
1990, 1993, 1994

UPD43256BGU-85L Summary of contents

  • Page 1

    Description The PD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations. ...

  • Page 2

    Ordering Information Part number Package PD43256BCZ-70L 28-pin plastic DIP (600 mil) PD43256BCZ-85L PD43256BCZ-70LL PD43256BCZ-85LL PD43256BGU-70L 28-pin plastic SOP (450 mil) PD43256BGU-85L PD43256BGU-70LL PD43256BGU-85LL PD43256BGU-A85 PD43256BGU-A10 PD43256BGU-A12 PD43256BGU-B10 PD43256BGU-B12 PD43256BGU-B15 PD43256BGW-70LL-9JL 28-pin plastic TSOP (I) PD43256BGW-85LL-9JL (8 13.4 mm) PD43256BGW-A85-9JL (Normal ...

  • Page 3

    Pin Configuration (Marking Side A14 I/O1 - I/O8 : Data inputs/outputs GND 28-pin plastic DIP (600 mil) PD43256BCZ 28-pin plastic SOP (450 mil) PD43256BGU A14 A12 ...

  • Page 4

    TSOP ( A11 A13 A14 8 A12 28-pin plastic TSOP (I) (8 A10 ...

  • Page 5

    Block Diagram A0 | A14 I/ GND Truth Table Remark : Don’t care Memory cell array 262,144 bits Input data Sense/Switch ...

  • Page 6

    Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input/Output voltage Operating ambient temperature Storage temperature Note –3.0 V (MIN.) (Pulse width 50 ns) Caution Exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. ...

  • Page 7

    DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2) Parameter Symbol Input leakage current I LI I/O leakage current I LO Operating supply current I CCA1 I CCA2 I CCA3 Standby supply current SB1 High level output ...

  • Page 8

    DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2) Parameter Symbol Input leakage current I LI I/O leakage current I LO Operating supply current I CCA1 I CCA2 I CCA3 Standby supply current SB1 High level output ...

  • Page 9

    AC Characteristics (Recommended operating conditions unless otherwise noted) AC Test Conditions Input waveform (Rise/fall time Input pulse levels 0 2.2 V: PD43256B-L, 43256B-LL 0 2.2 V: PD43256B-A, 43256B-B 1.5 V Output waveform 1.5 V Output load ...

  • Page 10

    Read Cycle (1/2) Parameter Symbol Read cycle time t RC Address access time access time t ACS OE access time t OE Output hold from address change output in low impedance t CLZ ...

  • Page 11

    Read Cycle Timing Chart Address (Input) CS (Input) OE (Input) High impedance I/O (Output) Remark In read cycle, WE should be fixed to high level ACS t CLZ OLZ Data ...

  • Page 12

    Write Cycle (1/2) Parameter Symbol Write cycle time end of write t CW Address valid to end of write t AW Write pulse width t WP Data valid to end of write t DW Data hold ...

  • Page 13

    Write Cycle Timing Chart 1 (WE Controlled) Address (Input) CS (Input (Input) I/O (Input/Output) Indefinite data out Cautions should be fixed to high level during address transition. 2. When I/O pins are in ...

  • Page 14

    Write Cycle Timing Chart 2 (CS Controlled) Address (Input) CS (Input) WE (Input) High impedance I/O (Input) Cautions should be fixed to high level during address transition. 2. When I/O pins are in the output state, ...

  • Page 15

    Low V Data Retention Characteristics CC L Version ( PD43256B- ˚C) A Parameter Symbol Data retention supply voltage V CCDR Data retention supply current I CCDR Chip deselection to data t CDR retention mode Operation ...

  • Page 16

    Data Retention Timing Chart t CDR 5.0 V Note 4 (MIN CCDR V (MAX.) IL GND Note A Version: 3 Version: 2.7 V Remark The other pins (address, OE, WE, I/Os) can be ...

  • Page 17

    Package Drawings 28 PIN PLASTIC DIP (600 mil NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center ...

  • Page 18

    PIN PLASTIC SOP (450 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition detail of lead end 14 ...

  • Page 19

    PLASTIC TSOP ( 13. NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold ...

  • Page 20

    PLASTIC TSOP ( 13. NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. ...

  • Page 21

    Recommended Soldering Conditions The following conditions (See table below) must be met when soldering PD43256B. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is ...

  • Page 22

    PD43256B ...

  • Page 23

    ... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...

  • Page 24

    ... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...