5M1270ZF256I5N Altera, 5M1270ZF256I5N Datasheet - Page 153

• Manufacturer Part Number: 5M1270ZF256I5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZF256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 211
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Operation Control
Figure 8–7. Selecting the Instruction Mode
December 2010 Altera Corporation
TAP_STATE
TMS
TDO
TCK
TDI
TEST_LOGIC/RESET
When the TAP controller is in the TEST_LOGIC/RESET state, the BST circuitry is
disabled, the device is in normal operation, and the instruction register is initialized
with IDCODE as the initial instruction. During device power up, the TAP controller
starts in this TEST_LOGIC/RESET state. In addition, the TAP controller may be forced to
the TEST_LOGIC/RESET state by holding TMS high for five TCK clock cycles. After the
TEST_LOGIC/RESET state, the TAP controller remains in this state as long as TMS
continues to be held high while TCK is clocked.
Figure 8–6
Figure 8–6. IEEE Std. 1149.1 Timing Waveforms
To start the IEEE Std. 1149.1 operation, select an instruction mode by advancing the
TAP controller to the shift instruction register (SHIFT_IR) state and shift in the
appropriate instruction code on the TDI pin.
Figure 8–7
the RESET state, TMS is clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR state.
Note to
(1) For timing parameter values, refer to the
RUN_TEST/IDLE
Figure 8–6
Captured
Driven
Signal
Signal
shows the timing requirements for the IEEE Std. 1149.1 signals.
shows the entry of the instruction code into the instruction register. From
to Be
to Be
SELECT_DR_SCAN
TMS
TDO
TCK
TDI
:
SELECT_IR_SCAN
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
CAPTURE_IR
DC and Switching Characteristics for MAX V Devices
t
JSH
SHIFT_IR
t
t
JPCO
JSCO
t
JPSU
(Note 1)
t
JSXZ
t
JPH
t
JPXZ
EXIT1_IR
MAX V Device Handbook
chapter.
8–7