AD7707BR Analog Devices Inc, AD7707BR Datasheet - Page 23

• Manufacturer Part Number: AD7707BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7707BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: 3V/5V, 1mW, 2?Channel, 16?Bit
• Package / Case: 20-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CALIBRATION SEQUENCES
The AD7707 contains a number of calibration options as
previously outlined. Table 25 summarizes the calibration types,
the operations involved, and the duration of the operations.
There are two methods of determining the end of calibration.
The first is to monitor when DRDY returns low at the end of
the sequence. DRDY not only indicates when the sequence is
complete, but also that the part has a valid new sample in its
data register. This valid new sample is the result of a normal
conversion, which follows the calibration sequence. The second
method of determining when calibration is complete is to
monitor the MD1 and MD0 bits of the setup register. When
Table 25. Calibration Sequences
Calibration Type
Self-Calibration
ZS System Calibration
FS System Calibration
MD1, MD0
0, 1
1, 0
1, 1
Calibration Sequence
Internal ZS calibration at selected gain +
Internal FS calibration at selected gain
ZS calibration on AIN at selected gain
FS calibration on AIN at selected gain
Rev. B | Page 23 of 52
these bits return to 0 (0 following a calibration command), it
indicates that the calibration sequence is complete. This method
does not give any indication of there being a valid new result in
the data register. However, it gives an earlier indication than
DRDY that calibration is complete. The duration to when the
Mode Bits (MD1 and MD0) return to 00 represents the
duration of the calibration carried out). The sequence to when
DRDY goes low also includes a normal conversion and a
pipeline delay, t
conversion. t
methods is given in the
P
Duration to Mode Bits
6 × 1/output rate
3 × 1/output rate
3 × 1/output rate
will never exceed 2000 × t
P
, to correctly scale the results of this first
Table 25
.
CLKIN
Duration to DRDY
4 × 1/output rate + t
9 × 1/output rate + t
4 × 1/output rate + t
. The time for both
AD7707
P
P
P