AD7707BR Analog Devices Inc, AD7707BR Datasheet - Page 8

• Manufacturer Part Number: AD7707BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7707BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: 3V/5V, 1mW, 2?Channel, 16?Bit
• Package / Case: 20-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7707
TIMING CHARACTERISTICS
AV
Table 4.
Parameter
f
t
t
Read Operation
Write Operation
1
2
3
4
5
6
7
CLKIN
CLKIN LO
CLKIN HI
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
See Figure 20 and Figure 21.
f
higher current than specified and possibly become uncalibrated.
The AD7707 is production tested with f
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
CLKIN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5
6
3, 4
duty cycle range is 45% to 55%. f
= DV
DD
1, 2
= 2.7 V to 5.25 V, AGND = DGND = 0 V; f
Limit at T
(B Version)
400
5
0.4 × t
0.4 × t
500 × t
100
0
120
0
80
100
100
100
0
10
60
100
100
120
30
20
100
100
0
CLKIN
CLKIN
CLKIN
MIN
, T
CLKIN
CLKIN
MAX
must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw
at 2.4576 MHz (1 MHz for some I
Unit
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
TO OUTPUT
PIN
Conditions/Comments
Master clock frequency: crystal oscillator or externally supplied for specified performance
Master clock input low time, t
Master clock input high time
DRDY high time
RESET pulse width
DRDY to CS setup time
CS falling edge to SCLK rising edge setup time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
SCLK falling edge to DRDY high
CS falling edge to SCLK rising edge setup time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
SCLK falling edge to data valid delay
DV
DV
DV
DV
Data valid to SCLK rising edge setup time
Data valid to SCLK rising edge hold time
CLKIN
50pF
DD
DD
DD
DD
= 2.4576 MHz; input logic = 0, Logic 1 = DV
= 5 V
= 3.0 V
= 5 V
= 3.0 V
Rev. B | Page 8 of 52
DD
tests). It is guaranteed by characterization to operate at 400 kHz.
I
I
SINK
SOURCE
(800µA AT V
100µA AT V
(200µA AT V
100µA AT V
1.6V
DD
DD
CLKIN
= 3V)
DD
= 5V
DD
7
= 3V)
= 5V
= 1/f
CLKIN
DD
) and timed from a voltage level of 1.6 V.
DD
OL
, unless otherwise noted.
or V
OH
limits.