AD7724ASTZ-REEL Analog Devices Inc, AD7724ASTZ-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7724ASTZ-REEL
• Description: FOUR CHANNEL SIGMA DELTA MODULATOR I.C.
• Manufacturer: Analog Devices Inc
• Type: Modulatorr

Specifications of AD7724ASTZ-REEL

• Resolution (bits): 15 b
• Sampling Rate (per Second): 250k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 2.85 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7724
TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
MCLK
DELAY
1
2
3
4
5
6
7
8
9
Sample tested at 25°C to ensure compliance.
Guaranteed by design.
SCLK (O)
DATA (O)
NOTE:
O SIGNIFIES AN OUTPUT
RESET (I)
DVAL (O)
MCLK (I)
Limit at T
(A Version)
100
15
14
67
0.45 × t
0.45 × t
15
10
10
20 × t
3
t
3
–t
8
MCLK
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
MCLK
MCLK
MIN
t
1
, T
t
8
1, 2
MAX
t
3
(AVDD = 5 V
REF2B = 2.5 V, unless otherwise noted.)
t
5
OUTPUT
PIN
TO
t
6
t
t
2
4
50pF
C
L
5%; DVDD = 5 V
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
t
9
I
1.6mA
I
200 A
OL
OH
t
7
5%; DVDD1 = 3 V
1.6V
Conditions/Comments
Master Clock Frequency
13 MHz for Specified Performance
MCLK to SCLK Delay
Master Clock Period
Master Clock Input High Time
Master Clock Input Low Time
Data Hold Time After SCLK Rising Edge
RESET Pulsewidth
RESET Low Time Before MCLK Rising
DVAL High Delay After RESET Low
Data Access Time After SCLK Falling Edge
Data Valid Time Before SCLK Rising Edge
5%; AGND = DGND = 0 V, REF2A =