AD8124ACPZ Analog Devices Inc, AD8124ACPZ Datasheet - Page 10

• Manufacturer Part Number: AD8124ACPZ
• Description: Triple Cat5 Cable Equalizer
• Manufacturer: Analog Devices Inc

Specifications of AD8124ACPZ

• Rohs Compliant: YES
• Bandwidth: 110MHz
• Supply Voltage Range: ± 4.5V To ± 5.5V
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): Yes
• Leaded Process Compatible: Yes
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8124
THEORY OF OPERATION
The AD8124 is a unity-gain, triple, wideband, low noise analog
line equalizer that compensates for losses in UTP and coaxial
cables up to 200 meters in length. The 3-channel architecture
is targeted at high resolution RGB applications but can be used
in HD YPbPr applications as well.
Three continuously adjustable control voltages, common
to the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The V
of high frequency peaking. V
used to compensate for frequency and cable-length dependent,
high frequency losses that are present due to the skin effect of
the cable. A second control pin, V
gain to compensate for low frequency flat losses present in the
cable. A third control, V
equalizer poles and can be linearly derived from V
in the Typical Performance Characteristics and Applications
Information sections, for UTP and coaxial cables. Finally, an
output offset adjust control, V
the output dc level.
The AD8124 has a high impedance differential input that makes
termination simple and allows dc-coupled signals to be received
directly from the cable. The AD8124 input can also be used in a
single-ended fashion in coaxial cable applications.
The AD8124 has a low impedance output that is capable of driving
a 150 Ω load. For systems where the AD8124 has to drive a high
impedance capacitive load, it is recommended that a small series
resistor be placed between the output and load to buffer the
capacitance. The resistor should not be so large as to reduce
the overall bandwidth to an unacceptable level.
PEAK
POLE
, is used to move the positions of the
input is used to control the amount
PEAK
OFFSET
GAIN
is the primary control that is
, allows the designer to shift
, is used to adjust broadband
PEAK
, as illustrated
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The AD8124 is designed such that systems that use short-to-
medium-length cables do not pay a noise penalty for excess gain
that they do not require. The high gain is only available for
longer length systems where it is required. This feature is built
into the V
Two comparators are provided on-chip that can be used for sync
pulse extraction in systems that use sync-on-common mode
encoding. Each comparator has very low output impedance and
can therefore be used in a source-only cable termination scheme
by placing a series resistor equal to the cable characteristic impedance
directly on the comparator output. Additional details are provided
in the Applications Information section.
INPUT COMMON-MODE VOLTAGE RANGE
CONSIDERATIONS
When using the AD8124 as a receiver, it is important to ensure
that its input common-mode voltage stays within the specified
range. The received common-mode level is calculated by adding
the common-mode level of the driver, the single-ended peak
amplitude of the received signal, the amplitude of any sync
pulses, and the other induced common-mode signals, such as
ground shifts between the driver and the AD8124 and pickup
from external sources, such as power lines and fluorescent lights.
See the Applications Information section for more details.
PEAK
control and is transparent to the user.