AD8124ACPZ Analog Devices Inc, AD8124ACPZ Datasheet - Page 13

• Manufacturer Part Number: AD8124ACPZ
• Description: Triple Cat5 Cable Equalizer
• Manufacturer: Analog Devices Inc

Specifications of AD8124ACPZ

• Rohs Compliant: YES
• Bandwidth: 110MHz
• Supply Voltage Range: ± 4.5V To ± 5.5V
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): Yes
• Leaded Process Compatible: Yes
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USING THE AD8124 WITH COAXIAL CABLE
The V
types of cable, including coaxial cable. Figure 17 presents the
recommended settings for V
AD8124 is used with good quality 75 Ω video cable. Figure 23
shows how to derive V
cable application where V
The op amp in the circuit that develops V
the offset of −0.62 V with a gain from V
unity. A passive offset circuit requires an offset injection voltage
that is much larger in magnitude than the available −5 V supply.
Clearly, the V
independently.
The AD8124 differential input can accept signals carried over
unbalanced cable, as shown in Figure 24, for an unbalanced
75 Ω coaxial cable termination.
DRIVING 75 Ω VIDEO CABLE WITH THE AD8124
When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). There are two options available for this.
One option is to place the additional gain of 2 at the drive end
by using the
The AD8148 has a fixed gain of 4 instead of the usual gain of 2
and thereby provides the required additional gain of 2 without
having to add additional amplifiers to the signal chain. The
AD8148 also contains sync-on-common-mode encoding. If
sync-on-common-mode is not required, it can be deactivated
on the AD8148 by connecting its sync level input to ground.
Figure 23. Deriving V
POLE
+5V
control allows the AD8124 to be used with other
V
PEAK
20kΩ
AD8148
INPUT FROM
10kΩ
75Ω CABLE
GAIN
POLE
Figure 24. Terminating a 75 Ω Cable
and V
control voltage can also be developed
5.11kΩ
1.16kΩ
1.24kΩ
triple differential driver to drive the cable.
POLE
GAIN
20Ω
PEAK
from V
–5V
and V
47.5kΩ
PEAK
originates from a low-Z source.
75Ω
24.3kΩ
PEAK
, V
GAIN
with Low-Z Source for the Coaxial Cable
POLE
V
V
V
POLE
GAIN
from V
PEAK
PEAK
, and V
AD8124
INPUT STAGE
GAIN
≈ 1.06 × V
≈ 0.76 × V
to V
is required to insert
PEAK
GAIN
GAIN
PEAK
PEAK
in a coaxial
that is close to
when the
– 0.62V
– 0.41V
Rev. 0 | Page 13 of 16
The other option is to include a triple gain-of-2 buffer, such as the
ADA4862-3, on the AD8124 RGB outputs, as shown in Figure 25
for one channel (power supplies not shown). The ADA4862-3
provides the gain of 2 that compensates for the double-
termination loss.
DRIVING A CAPACITIVE LOAD
When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8124
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.
POWER SUPPLY FILTERING
External power supply filtering between the system power supplies
and the AD8124 is recommended in most applications to prevent
supply noise from contaminating the received signal as well as
to prevent unwanted feedback through the supplies that may
cause instability. Figure 26 shows that the AD8124 power supply
rejection decreases with increasing frequency. These plots are
for the lowest control settings and shift upward as the peaking
is increased.
FROM AD8124
ONE VIDEO
OUTPUT
–10
–20
–30
–40
–50
–60
10
0
100k
Figure 25. Using the ADA4862-3 on AD8124 Outputs
V
V
V
GAIN
PEAK
POLE
ONE CHANNEL OF ADA4862-3
= 0V
= 0V
= 0V
500 Ω
Figure 26. PSRR vs. Frequency
1M
500 Ω
FREQUENCY (Hz)
10M
75 Ω
Z
0
= 75Ω
100M
+PSRR
–PSRR
AD8124
75Ω