AD9222BCPZRL7-65 Analog Devices Inc, AD9222BCPZRL7-65 Datasheet - Page 34

IC,A/D CONVERTER,OCTAL,12-BIT,LLCC,64PIN

AD9222BCPZRL7-65

Manufacturer Part Number
AD9222BCPZRL7-65
Description
IC,A/D CONVERTER,OCTAL,12-BIT,LLCC,64PIN
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9222BCPZRL7-65

Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Serial, SPI™
Number Of Converters
8
Power Dissipation (max)
950.5mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9222-65EBZ - BOARD EVALUATION AD9222 65MSPSAD9222-50EBZ - BOARD EVALUATION FOR AD9222
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9222BCPZRL7-65
Manufacturer:
AD
Quantity:
1 001
AD9222
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface
between the user’s programming device and the serial port of
the AD9222. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should
be taken to ensure that proper V
same load for each AD9222, Figure 83 shows the number of SDIO
pins that can be connected together and the resulting V
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
0
10
NUMBER OF SDIO PINS CONNECTED TOGETHER
20
Figure 83. SDIO Pin Loading
30
40
OH
50
levels are met. Assuming the
60
70
80
90
OH
100
level.
Rev. D | Page 34 of 60
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers, providing the user with an
alternative method, other than a full SPI controller, to program
the ADC (see the AN-812 Application Note).
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.

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