AD9222BCPZRL7-65 Analog Devices Inc, AD9222BCPZRL7-65 Datasheet - Page 41

• Manufacturer Part Number: AD9222BCPZRL7-65
• Description: IC,A/D CONVERTER,OCTAL,12-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9222BCPZRL7-65

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 950.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9222-65EBZ - BOARD EVALUATION AD9222 65MSPSAD9222-50EBZ - BOARD EVALUATION FOR AD9222
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9222 Rev. A evaluation board.
•
•
•
•
•
POWER: Connect the switching power supply that is
provided with the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 150 MHz of bandwidth (see Figure 87). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
VREF: VREF is set to 1.0 V by tying the SENSE pin to ground,
R317. This causes the ADC to operate in 2.0 V p-p full-scale
range. A separate external reference option using the
or
R312 and R313 and remove C307. Proper use of the VREF
options is noted in the Voltage Reference section.
RBIAS: RBIAS has a default setting of 10 kΩ (R301) to
ground and is used to set the ADC core bias current.
CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T401) that adds a very
low amount of jitter to the clock path. The clock input is
Figure 87. Evaluation Board Full-Power Bandwidth, AD9222-50
–10
–12
–14
–16
–18
–2
–4
–6
–8
ADR520
0
0
50
is also included on the evaluation board. Populate
100
150
FREQUENCY (MHz)
–3dB CUTOFF = 150MHz
200
250
300
350
400
450
ADR510
500
Rev. D | Page 41 of 60
•
•
•
•
•
•
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U401). Populate R406 and
R407 with 0 Ω resistors and remove R215 and R216 to
disconnect the default clock path inputs. In addition, populate
C205 and C206 with a 0.1 μF capacitor and remove C409 and
C410 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the
for more information about these and other options.
and can act as the primary clock source. The setup is quick
and involves installing R403 with a 0 Ω resistor and setting
the enable jumper (J401) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC401) to check the ADC performance.
PDWN: To enable the power-down feature, short J301 to
the on position (AVDD) on the PDWN pin.
SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J304. If J304 is tied to AVDD during
device power-up, Test Pattern 1000 0000 0000 is enabled. See
the SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J303. If J303 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J302 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J302
to AVDD.
Non-SPI Mode: For users who wish to operate the DUT
without using SPI, remove Jumpers J302, J303, and J304.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins
from the control bus, allowing the DUT to operate in its
simplest mode. Each of these pins has internal termination
and will float to its respective level.
D + x, D − x: If an alternative data capture method to the setup
shown in Figure 90 is used, optional receiver terminations,
R318 and R320 to R328, can be installed next to the high
speed backplane connector.
In addition, an on-board oscillator is available on the OSC401
AD9515
AD9222
data sheet