AD976AR Analog Devices Inc, AD976AR Datasheet - Page 7

• Manufacturer Part Number: AD976AR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD976AR

• Package/case: 28-SOIC
• Features: 16?Bit, Serial, 100kSPS ADC
• Interface Type: Parallel
• Leaded Process Compatible: No
• Number Of Bits: 16
• Number Of Channels: 1
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Sampling Rate (per Second): 200k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD976CB - BOARD EVAL FOR AD976EVAL-AD976ACB - BOARD EVAL FOR AD976A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
TRANSIENT RESPONSE
The time required for the AD976/AD976A to achieve its rated
accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
Signal-to-(Noise Plus Distortion Ratio) (S/[N+D])
S/(N+D) is the measured signal-to-noise plus distortion ratio at
the output of the ADC. The signal is the rms magnitude of the
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the sampling rate
excluding dc. The S/(N+D) is dependent upon the number of
quantization levels. The more levels, the lower the quantization
noise. The theoretical S/(N+D) for a sine wave input signal can
be calculated using the following:
where N is the number of bits.
Thus, for an ideal 16 bit converter, S/(N+D) = 98 dB.
The output spectrum from the ADC is evaluated by applying a
low noise, low distortion sine wave signal to the V
sampling at a 200 kHz throughput rate. By generating a Fast
Fourier Transform (FFT) plot, the S/(N+D) data can then be
obtained. Figure 10 shows a typical 2048-point FFT plot with
an input signal of 45 kHz and a sampling rate of 200 kHz. The
S/(N+D) obtained from this graph is 86.23 dB.
Since the measured S/(N+D) is less than the theoretical value, it
is possible to get a measure of performance expressed in effective
number of bits (ENOB).
Thus for an input signal of 45 kHz, the typical ENOB is 14.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. For the AD976/AD976A, THD is
defined as:
REV. C
S/(N+D) = (6.02N + 1.76) dB
THD dB
ENOB = ((S/(N+D) – 1.76) / 6.02)
20
log
V
2
2
V
3
2
V
V
1
4
2
V
5
2
IN
V
pin and
6
2
(1)
–7–
where V
V
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum shown in Figure 10 and is seen there
as –105.33 dB.
Spurious Free Dynamic Range (SPFD)
The spurious free dynamic range is defined as the difference, in
dB, between the peak spurious or harmonic component in the
ADC output spectrum (up to F
value of the fundamental. Normally, the value of this specification
will be determined by the largest harmonic in the spectrum. The
typical SPFD for the AD976/AD976A is –100 dB and can be
seen in Figure 10.
FUNCTIONAL DESCRIPTION
The AD976/AD976A is a high speed, low power, 16-bit sam-
pling, analog-to-digital converter that can operate from a single
+5 volt power supply. The AD976/AD976A uses laser trimmed
scaling input resistors to provide an industry standard 10 volt
input range. With a 100/200 kSPS throughput rate and a paral-
lel interface, the AD976/AD976A is capable of connecting di-
rectly to digital signal processors and microcontrollers.
The AD976/AD976A employs a successive-approximation
technique to determine the value of the analog input voltage.
Instead of using the traditional laser-trimmed resistor-ladder
approach, however, this device uses a capacitor array charge
distribution technique. Binary weighted capacitors subdivide the
input sample to perform the actual analog-to-digital conversion.
The capacitor array eliminates variation in the linearity of the
device due to temperature-induced mismatches of resistor val-
ues. As a result of having an on-chip capacitor array, there is no
need for additional external circuitry to perform the sample/hold
function.
Initial errors in capacitor matching are eliminated at the time of
manufacturing. Calibration coefficients are calculated that cor-
rect for capacitor mismatches and are stored in on-chip thin-film
resistors that act as ROM. As a conversion is occurring, the appro-
priate calibration coefficients are read out of ROM. The accumu-
lated coefficients are then used to adjust and improve conversion
accuracy. Any initial offset error is also trimmed out during
factory calibration. With the addition of an onboard reference
the AD976/AD976A provides a complete 16-bit A/D solution.
4
, V
5
and V
1
is the rms amplitude of the fundamental, and V
6
are the rms amplitudes of the second through
S
/2 and excluding dc) and the rms
AD976/AD976A
2
, V
3
,